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| fedl7344c/e/j-05 issue date: jan 20, 2015 ml7344c/e/j sub-ghz(160mhz to 510mhz) band short range wireless transceiver ic 1/154 overview ml7344c/e/j is a narrow band sub-ghz ic that integrates rf part, if part, modem part and host interface part in single-chip. it supports various frequency band from 160mhz to 510mhz. ml7344c can output 100mw (20dbm) transimittion power and it suits for the smart-meter in chinese market. ml7344e is suitable for fmode (434mhz) or n mode (169mhz) of wireless m-bus system. ml7344j is suitable for security radio system type iii or iv of the rcr std-30 and specified low-power radio station in 426 mhz operation of the arib std-t67. ml7406 and ml7344 have the same package, pins assignment and major registers. 1 10 100 1000 frequency [mhz] 250 500 750 0 ml7406 series rf: 750mhz to 960mhz rate: 1.2kbps to 500kbps (fsk/gfsk) channel spacing: 100 khz to 1.6mhz wireless m-bus ieee802.15.4g (fec not supported) arib std-t108 1000 ml7344 series rf: 160mhz to 510mhz rate: 1.2kbps to 15kbps (fsk/gfsk) channel spacing: 25 khz wireless m-bus arib std-t67 ml7406 series ml7344 series data rate [kbps] (32pin wqfn) a rib std t67 (426/429 mhz) wireless m-bus (868mhz) wireless m-bus (169mhz) ieee802.15.4g (780 to 960mhz)
fedl7344c/e/j-05 ml7344c/e/j 2/154 features ? frequency range: 160 ? 510mhz ? ml7344c is able to use as communication unit of q_gdw374.3 (china) ml7344e is able to use as f mode or n mode of the wirelss m-bus system. ml7344j is able to use as type iii or iv security radio of rcr std-30 and arib std-t67 in 426 mhz operation. (japan) ? high accurate modulation implemented by direct modulation scheme using fractional-n pll. ? multiple modulation scheme : gfsk/gmsk, fsk/msk ? configurable data ratres from 1.2kbps to 15 kbps ? supports nrz code, manchester code and 3 out of 6 code. ? programmable modulation frequency deviation ? polarity conversion for tx and rx data bits ? on chip 26mhz oscillation circuit implemented (ml7344xc x=c, e or j) supports 26mhz tcxo input. (ml7344xt, x=c, e or j) note: the ordering product name is different from supporting clock source. ? on chip low speed rc oscillation circuit. ? oscillation frequecy tuning function implemented. (ml7344xc x=c, e or j) ? frequency tuning function (frequency fine tuning by oscillation circuit and fractional-n pll) ? built in power amp (pa) and power control function programmable from 100mw, 20mw and 10mw (ml7344c) programable from 20mw,10mw and 1mw (ml7344e/j) ? fine output power tuning function implemented. (tune 0.2db) ? tx ramp control function implemented ? high speed carrier checking function ? support external pa ? receive signal strength indicator (rssi) repor ting function and threshold comparison function ? built-in afc function ? synchronous serial peri pheral interface (spi) ? auto wake-up and auto sleep function are implemented ? 2 genral purpose timers are implemented ? test pattern generation (pn9, cw, 0/1, all-1, all-0 pattern) fedl7344c/e/j-05 ml7344c/e/j 3/154 ? packet mode function ? support 2 wireless m-bus packet format. (format a and b) ? support general packet format (format c) ? max packet length 255 bytes (format a and b)and 2047 bytes (format c) ? 64 byte tx and rx buffer are implemented ? preamble pattern detection function (preamble length can be prgrammable between 1 to 4 byte) ? programmable tx preamble length (max 16383 byte) ? id code or sfd detection function (max 4 byte x 2codes, available for tx and rx) ? progrmable crc generate function for crc32, crc16 and crc8 ? whitenning function ? address filtering function checking c-fieled, m-field and a field of wireless m-bus packet (en13575-4:2011) ? supply voltage 1.8v to 3.6v outpur power is set at 1mw 2.1v to 3.6v output power is set at 10mw 2.6v to 3.6v output power is set at 20mw 3.3v to 3.6v output power is set at 100mw ? operating temperature -40 to +85 ? c ? current consumption (operation at 400mhz band) deep sleep mode: 0.1 ua (typ) sleep mode1 0.4 ua (typ) (maintain register values) sleep mode2 0.53 ua (typ) (maintain register values and fifo data) idle mode 0.6 ma (typ) tx 100mw 90 ma (typ.) 20mw 28 ma (typ.) (ml7344e/j) 45 ma (typ.) (ml7344c) 10mw 22 ma (typ.) 1mw 8.8 ma (typ.) rx 6.2 ma (typ.) ? package 32 pin wqfn 5.0mm x 5.0mm x 0.8mm pb free, rohs compliant ordering guide ml7344 x y gdz05bl x =c: 470mhz to 510mhz e: 160mhz to 180mhz j: 426mhz to 434mhz y =c: crystal input t: tcxo input fedl7344c/e/j-05 ml7344c/e/j 4/154 description convention 1) numbers description ?0xnn? indicates hexadecimal and ?0bnn? indicates binary example: 0x11=17 (decimal), 0b11=3 (decimal) 2) register description [ fedl7344c/e/j-05 ml7344c/e/j 5/154 block diagram fig.1 block diagram lna mix bpf limiter pa 100mw/20mw or 20mw/1mw lo pll vco rf ml7344c/e/j s p i phy rssi fifo reg_out reg_core osc xin xout i r c bb sclk sdo sdi scen gpio0 v bg resetn tcxo ext_clk lna_p pa_out reg.(pa) reg. reg_pa regpdin v b_ext lp ind1 ind2 ed_val demod rf_manager digital mod fmap wakeup timer gpio1-3 general timer1/2 a _mon fedl7344c/e/j-05 ml7344c/e/j 6/154 pin configuration package: 32pin wqfn lna_p a_mon vdd_pa reg_pa pa_out gpio3 gpio2 gpio1 24 23 22 21 20 19 18 17 vdd_rf 25 16 gpio0 lp 26 15 sdi vdd_cp 27 14 scen ind1 28 13 sclk gnd_vco 29 12 sdo ind2 30 11 regpdin vb_ext 31 10 ext_clk vdd_vco 32 9 vddio 12345678 vdd_reg vbg reg_out reg_core xin xout(tcxo, spxo) n.c resetn Ypkg gnd (t.b.d.) Ypkg gnd Ypkg gnd (t.b.d.) Ypkg gnd fig.2 pin assignment note: pattern shown in the centre of the chip is located at bottom side of the chip (gnd pad) gnd pad xin (n.c) fedl7344c/e/j-05 ml7344c/e/j 7/154 pin definitions symbols i : digital input o : digital output is : shmidt trigger input io : digital input/output i a : analog input o a : analog output 1 o ah : analog output 2 io a : analog input/output o rf : rf output v ddio : i/o power supply v ddrf : rf power supply gnd : ground rf and analog pins pin pin name reset state i/o active level function 20 pa_out ? o rf ? rf antenna output 23 a_mon ? o a ? temperature information output (*1) 24 lna_p ? i a ? rf antenna input 26 lp ? io a ? pin for loop filter 28 ind1 ? io a ? pin for vco tankl inductor 30 ind2 ? io a ? pin for vco tank inductor 31 vb_ext ? io a ? pin for smothing capacitor for internal bias *1 this pin can be configured by [mon_ctrl:b0 0x4d] register, no signal assigned as default setting. fedl7344c/e/j-05 ml7344c/e/j 8/154 spi interface pins pin pin name reset state i/o active level function 12 sdo o/l o h or l spi data output or dclk (*1) 13 sclk i i s p or n spi clock input 14 scen i i s l spi chip enable l: enable h: disable 15 sdi i i s h or l spi data input or dio (*1) *1 please refer to ?dio function? regulator pins pin pin name reset state i/o active level function 2 vbg (*1) ? o ah ? pin for decouppling capacitor 3 reg_out (*1) ? o ah ? requlator1 ouput (typ. 1.5v) 4 reg_core ? o a ? requlator2 ouput (typ. 1.5v) 11 regpdin i i h power down control pin for regulator fix to ?l? for nomal use. ?h? is for deep sleep mode. 21 reg_pa (*1) ? o ah ? regulator output for pa block *1 these pin will output 0v in the sleep state. fedl7344c/e/j-05 ml7344c/e/j 9/154 miscellaneous pins pin pin name reset state i/o active level function 5 xin n.c.(*2) i ? i a ? p or n ? 26mhz crystal pin1 (note) in case of tcxo, it must be open. 6 xout tcxo(*2) o o a i a i p or n 26mhz crystal pin 2 or tcxo input 8 resetn i i s l reset l: hardware reset enable (forcing reset state) h: normal operation 10 ext_clk i io p or n digital i/o (*3) reset state: external rtc (32khz) input. [ml7344e/j] external pa control signal output. [ml7344c] 16 gpio0 o/h io or od(*1) h or l digital gpio (*4) reset state: interrupt indication signal output 17 gpio1 o/l io or od(*1) h or l digital gpio (*5) reset state: clock output 18 ant_sw/ gpio2 o/l io or od(*1) h or l digital gpio (*6) reset state: antenna diversity selection control signal 19 trx_sw/ gpio3 o/l io or od(*1) h or l digital gpio (*7) reset state: tx ?rx selection signal control (note) *1 od is open drain output. *2 the following pin names are different depend on products. pin no. ml7344c ml7344t 5 xin n.c. 6 xout tcxo (note) *1 in case of using tcxo, set tcxo_en=0b1. please make sure only one of the register tcxo_en, xtal_en is set to 0b1. *2 for ml7344jy, the initial value of the register tcxo_en is 0b1. in case of using ml7344jc, the register xtal_en([clk_set2: b0 0x03(4)])=0b1 must be programmed first. *3 for ml7344cy, the initial value of the register xtal_en is 0b1. in case of using ml7344ct, the register tcxo_en([clk_set2: b0 0x03(6)])=0b1 must be programmed first. *4 please refer to [extclk_ctr: b0 0x52] register. *5 please refer to [gpio0_ctrl: b0 0x4e] register *6 please refer to [gpio1_ctrl: b0 0x4f] register *7 please refer to [gpio2_ctrl: b0 0x50] register *8 please refer to [gpio3_ctrl: b0 0x51] register fedl7344c/e/j-05 ml7344c/e/j 10/154 power supply/gnd pins pin pin name reset state i/o active level function 1 vdd_reg ? v ddio ? power supply pin for regulator (input voltage: 1.8v to 3.3v) 9 vddio ? v ddio ? power supply for digital i/o (input voltage: 1.8 to 3.6v) 22 vdd_pa ? v ddio ? power supply for pa block (input voltage: 18 to 3.6v, depending on tx mode) 25 vdd_rf ? v ddrf ? power supply for rf blocks (reg-out is connected, typ.1.5v) 27 vdd_cp ? v ddrf ? power supply for charge pump (reg-out is connected, typ.1.5v) 32 vdd_vco ? v ddrf ? power supply for vco (reg_out is connected, typ.1.5v) 29 gnd_vco ? gnd ? gnd for vco unused pins treatment unused pins treatments are as follows: unused pins treatment pin name pins number recommended treatment n.c. 5 open n.c. 7 gnd or open ext_clk 10 gnd a_mon 23 gnd gpio0 16 open gpio1 17 open gpio2 18 open gpio3 19 open (note) *1 if input pins are high-impedence state and leave open, excess current could be drawn. care must be taken that unused input pins and unused i/o pins should not be left open. *2 after reset, gpio1 pin is clk_out function. if this function is not used, the clock must to be disabled by setting 0b000 to gpio1_io_cfg[2:0] ([gpio1_ctrl: b0 0x4f (2-0)]). if this pin is left open while outputing clock signal, it may affect rx sensitivity. fedl7344c/e/j-05 ml7344c/e/j 11/154 electrical characteristics absolute maximum ratings ta=-40 ? c to +85 ? c and gnd=0v is the typical conditoin if not defined specific condition. item symbol condition rating unit i/o power supply v ddio -0.3 to +4.6 v rf power supply v ddrf -0.3 to +2.0 v rf input power p rfi antenna input in rx 0 dbm rf output voltage v rfo pa_out(#20) -0.3 to +4.6 v rf output voltage[ml7344c] v rfo pa_out(#20) duty cycle of transmission at +20dbm output <1 % -0.3 to +7.7 v voltage on analog pins 1 v a -0.3 to +2.0 v voltage on analog pins 2 v ah -1.0 to +4.6 v voltage on digital pins v d -0.3 to +4.6 v digital input current idi -10 to +10 ma digital output current ido -8 to +8 ma power dissipation pd ta= +25 ?c 1.2 w storage temperature tstg ? -55 to +150 ?c fedl7344c/e/j-05 ml7344c/e/j 12/154 recommended operating conditions item symbol conditions min typ. max unit power supply (i/o) v ddio vdd_io, vdd_reg pins 1.8 3.3 3.6 v vdd_pa pin tx power = 1mw 1.8 3.3 3.6 v vdd_pa pin tx power = 10mw 2.1 3.3 3.6 v vdd_pa pin tx power = 20mw 2.6 3.3 3.6 v power supply (pa) v ddpa vdd_pa pin tx power = 100mw 3.3 - 3.6 v ambient temperature t a - -40 +25 +85 oc digital input rising time t ir digital input pins (*1) - - 20 ns digital input falling time t if digital input pins (*1) - - 20 ns digital output loads c dl all digital output pins - - 20 pf master clock frequency f mck1 (*2) - 26 - mhz master clock accuracy a cmck (*3) -10 +10 ppm tcxo input voltage v tcxo dc cut (ml7344xt) 0.8 - 1.5 vpp spi clock frequency f sclk sclk pin 0.032 2 16 mhz spi clock duty ratio d sclk sclk pin 45 50 55 % rf channel frequency f rf ml7344c ml7344e ml7344j 470 160 315 - - - 510 180 450 mhz (*1) those pins with symbol i, is at pin definition section (*2) xin and xout pin (ml7344xc), tcxo pin (ml7344xt) (*3) this difinition is the specification of rf communication availability, not the system requirement. use the appropriate frequency accuracy under each specificaton requirement as below. specification required accuracy rcr std-30 type iii (japan) 10 ppm rcr std-30 type iv (japan) 4 ppm wireless m-bus n mode 1.5khz (8.5 ppm, 4.8kbps) 2.0khz (11.803 ppm, 2.4kbps) wireless m-bus f mode 16 ppm fedl7344c/e/j-05 ml7344c/e/j 13/154 power consumption item symbol conditions min typ. (*2) max(*3) unit i dd_dslp deep sleep mode - 0.1 11 (0.8) a i dd_slp1 sleep mode 1 (*4) - 0.4 23 (1.6) a i dd_slp2 sleep mode 2 (*4) - 0.53 25.8 (1.9) a i dd_slp3 sleep mode 3 (*4) - 0.7 26 (2.1) a i dd_slp4 sleep mode 4 (*4) - 2.14 28 (4.1) a i dd_idle idle mode(*5) - 0.6 - ma i dd_rx rf rx mode (*6)(*7) low _ rate _ en ([ clk _ set2: - 5.9 - ma i dd_tx1 rf tx mode (1mw) (*6) for ml7344e/j - 8.8 - ma i dd_tx10 rf tx mode (10mw) (*6) - 22.0 - ma for ml7344e/j (*6) - 28.0 - ma i dd_tx20 rf tx mode (20mw) for ml7344c (*7) - 45.0 - ma i dd_tx100 rf tx mode (100mw) (*7) for ml7344c - 90 - ma power consumption (*1) i dd_xtal x?tal oscillator circuit (*8) - 0.3 - ma (*1) power consumption is sum of current consumption of all power supply pins (*2) ?typ? value is centre value under condition of vddio=3.3v, 25 ? c. (*3) () is a reference maximum value under condition of 25 ? c (*4) the definition od each sleep mode is shown in following table. mode. register fifo rc osc. (32khz) low clock timer sleep mode 1 not retain not retain off - sleep mode 2 retain retain off - sleep mode 3 retain retain external input on sleep mode 4 retain retain on on (*5) under condition of using tcxo. (*6) under condition of data receiving sp eed at 9.6 kbps and 426 mhz operation. (*7) under condition of data receiving sp eed at 9.6 kbps and 490 mhz operation. fedl7344c/e/j-05 ml7344c/e/j 14/154 (*8) when using ml7344xc, power consumptions of each mode exluded deep sleep and sleep are added i dd_xtal . dc characteristics item symbol conditions min typ. (*2) max unit vih1 digital input/inout pins v ddio *0.75 - v ddio v voltage input high vih2 xin pin 1.35 - 1.5 v vil1 digital input/inout pins 0 - v ddio *0.18 v voltage input low vil2 xin pin 0 - 0.15 v schmit trigger threshold high level vt+ digital pins with shmitt trigger gate - 1.2 v ddio *0.75 v schmit trigger threshold low level vt- digital pins with shmitt trigger gate v ddio *0.18 0.8 - v iih1 digital input pins -1 - 1 a iil1 digital input pins -1 - 1 a input leakage current iil2 xin pin -0.3 - 0.3 a iozh ext_clk, gpio0-3 pins -1 - 1 a tri-state output leakage current iozl ext_clk, gpio0-3 pins -1 - 1 a voltage ouput level h voh ioh=-4ma v ddio *0.8 - v ddio v voltage ouput evel l vol iol=4ma 0 - 0.3 v main_reg reg_core and reg_outpin when in mode other than 1.4 1.5 1.6 v regulator output voltage sub_reg reg_core pin when in sleep mode 0.95 1.5 1.65 v cin input pins - 6 - pf cout output pins - 9 - pf crfio rf inout pins - 9 - pf pin capacitance cai analog input pins - 9 - pf fedl7344c/e/j-05 ml7344c/e/j 15/154 rf characteristics data rate : 1.2 kbps to 15 kbps modulation scheme : 2-gfsk/ 2-fsk channel spacing : 25khz definisiton point : ant connector of ml7344 rf board. [rf frequency] item condition min typ. max unit ml7344c 470 - 510 mhz ml7344e 160 - 180 mhz ml7344j lna_p,pa_out pins 315 - 450 mhz note:1) support 160 mhz to 510 mhz by changing l and c components between ind1 and ind2 pins 2) integer multiples of the master clock frequency and its around frequency can not be used. please refer section of ?programing channel frequency ? [tx characteristics] 170mhz and 426mhz band (160mhz to 180mhz, 315mhz to 450mhz) [ml7344e/j] item condition min typ. max unit 20mw(13dbm) mode 10 13 13.8 dbm 10mw(10dbm) mode 7 10 10.8 dbm tx power 1mw(0dbm) mode -3 0 0.8 dbm frequency deviation setting range [fdev] 0.025 - 400 khz occupied bandwidth 9600 bps (pn9), fdev=3 khz band including 99% power 8.5 - 11.8 khz adjacent channel power 9600bps (pn9), fdev=3 khz offset:25 khz 8 khz band - - -40 db +10dbm output 9600 bps (pn9). fdev = 3 khz total power from 62.5 khz to 162.5khz offset - - -26 dbm spurious emission level harmonics +10dbm output with lc trap filter 9600 bps (pn9). fdev = 3 khz - - -26 dbm fedl7344c/e/j-05 ml7344c/e/j 16/154 470mhz band(470mhz to 510mhz) [ml7344c] item condition min typ. max unit 100mw(20dbm) mode 18.5 20 23 dbm tx power 20mw(13dbm) mode 10 13 16 dbm frequency deviation (fdev) range 0.025 - 400 khz occupied bandwidth 9600 bps (pn9), fdev=3 khz band including 99% power 8.5 - 11.8 khz spurious emission level harmonics +20dbm output with lc trap filter - - -36 dbm fedl7344c/e/j-05 ml7344c/e/j 17/154 [rx characteristics] 426mh z band (315mhz to 450mhz) [ml7344j] item condition min typ. max unit 4.8 kbps, fdev=3khz - -115 -108 dbm 9.6 kbps, fdev=3khz - -114 -107 dbm 4.8 kbps, fdev=3khz high gain mode - -118 -111 dbm minimum rx sensitivity ber<0.1% 9.6 kbps, fdev=3khz high gain mode - -117 -110 dbm 12.5 khz - 3 - db 25 khz 30 33 - db adjacent channel rejection 50 khz - 36 - db 1 mhz offset - 69 - db 2 mhz offset - 72 - db 6 mhz offset - 75 - db 10 mhz offset - 80 - db blocking (426mhz operation) -400khz offset (image frequency), ta=25 oc after i/q adjustment 30 40 - db - -115 - dbm minimum power detection level rfmin in figure of rssi characteristics*1 high gain mode - -120 - dbm - 40 - db power detection range dynamic range in figure of rssi characteristics*1 high gain mode - 35 - db spurious emission level compliant with fcc, arib, etsi standard - - -54 dbm *1. rssi characteristics as shown follow. fedl7344c/e/j-05 ml7344c/e/j 18/154 470mhz band(470mhz to 510mhz) [ml7344c] high gain mode item condition min typ. max unit 4.8 kbps, fdev=3khz (ber<0.1%) - -116 - dbm 9.6 kbps, fdev=3khz (ber<0.1%) - -115 - dbm 4.8 kbps, fdev=3khz (ber<1%) - -118 - dbm minimum rx sensitivity 9.6 kbps, fdev=3khz (ber<1%) - -117 - dbm adjacent channel rejection 200khz - 55 - db 1 mhz offset - 65 - db 2 mhz offset - 66 - db 6 mhz offset - 71 - db 10 mhz offset - 73 - db blocking -400khz offset (image frequency), ta=25 oc after i/q adjustment - 40 - db minimum power detection level rfmin in figure of rssi characteristics*1 - -120 - dbm power detection range dynamic range in figure of rssi characteristics*1 - 35 - db spurious emission level compliant with fcc, arib, etsi standard - - -54 dbm rf input level ed -60 -80 -100 rfmin rfma x measured point calculated point no in p ut d y namic ran g e edmax edmin fedl7344c/e/j-05 ml7344c/e/j 19/154 170mhz band [ml7344e] item condition min typ. max unit 4.8 kbps, fdev=3khz - -115 - dbm 9.6 kbps, fdev=3khz - -114 - dbm 4.8 kbps, fdev=3khz high gain mode - -118 - dbm minimum rx sensitivity ber<0.1% 9.6 kbps, fdev=3khz high gain mode - -117 - dbm 12.5 khz - 3 - db 25 khz - 33 - db adjacent channel rejection 50 khz - 36 - db 1 mhz offset - 69 - db 2 mhz offset - 72 - db 6 mhz offset - 75 - db 10 mhz offset - 80 - db blocking (426mhz operation) -400khz offset (image frequency), ta=25 oc after i/q adjustment - 40 - db - -115 - dbm minimum power detection level rfmin in figure of rssi characteristics*1 high gain mode - -120 - dbm - 40 - db power detection range dynamic range in figure of rssi characteristics*1 high gain mode - 35 - db spurious emission level compliant with fcc, arib, etsi standard - - -54 dbm rc oscillator circuit characteristics item symbol condition min typ. max unit oscillation frequency f rcosc - 44 - khz fedl7344c/e/j-05 ml7344c/e/j 20/154 spi interface characteristics item symbol condition min typ. max unit sclk clock frequency f sclk 0.032 2 16 mhz scen input setup time t scensu 30 ? ? ns scen input hold time t scenh 30 ? ? ns sclk high pulse width t sclkh 28 ? ? ns sclk low pulse width t sclkl 28 ? ? ns sdi input setup time t sdisu 5 ? ? ns sdi input hold time t sdih 15 ? ? ns scen negate time t scenni 200 ? ? ns sdo output delay time t sdodly load capacitance cl=20pf ? ? 22 ns note: all timing parameter is defined at voltage level of v ddio * 20% and v ddio * 80%. scen sclk sdo sdi msb in bits6-1 lsb in f sclk t sclkh t sdisu t sclkl msb out bits6-1 lsb t scenh t sdodly t sdih t scensu scen t scenni fedl7344c/e/j-05 ml7344c/e/j 21/154 dio interface characteristics item symbol condition min typ. max unit dio input setup time t disu 1 - - s dio input hold time t dih 0 - - ns dio output hold time t doh 20 - - ns dclk frequency accuracy in tx (*1) f dclk_tx (*3) - (*3) khz dclk frequency accuracy in rx (*2) f dclk_rx -30 - +30 % dclk output duty ratio (tx) d dclk_tx 45 - 55 % dclk output duty ratio (rx) d dclk_rx load capacitance cl=20pf 30 - 70 % (*1) dclk clock frequency in tx mode will be varied depending on the variance of master clock frequency. (*2) dclk clock frequency in rx mode will be varied by reproduced clock and its jitter. (*3) these values are equal to the accuracy of the master clock frequency note: all timing parameter is defined at voltage level of v ddio * 20% and v ddio * 80%. dclk dio(input) valid valid valid f dclk _ t x / f dclk _ r x t disu t dih dio(output) valid valid valid t doh fedl7344c/e/j-05 ml7344c/e/j 22/154 clock output characteristics ml7344x has configurable clock output function. it is controlled by [mon_cntrl: b0 0x4d] register and [gpion_ctrl: b0 0x4e-0x51)] registers (n=0 to 3),. default settign is the 3.33mhz clock is output from gpio1. item symbol condition min typ. max unit clock output frequency f clkout 0.0064 3.33 26 mhz 8.66 mhz 33 - 67 % clock output duty ratio d clkout load capacitance cl=20pf other than 8.66 mhz 48 50 52 % gpion f clkout fedl7344c/e/j-05 ml7344c/e/j 23/154 reset characteristics item symbo condition min typ. max unit resetn delay time (power on) t rdl1 all power supply pins (after power on) 0.5 - - ms resetn pulse period when starting from vddio=0v t rpw1 200 - - ns resetn pulse period 2 when starting from vddio 0v t rpw2 vddio > 1.8v should be required. 1.5 - - ms resetn input delay time (when ml7344 start up from vddio 0v) t rdl2 vddio > 1.8v 1 - - s resetn rising time t rrst - - 1 ms note: when ml7344 start up from vddio 0v, resetn pulse should be asserted after vddio becomes over 1.8v. vddio reset t rdl1 t rpw1 t rpw2 less than 1.8v t rdl2 vdd level gnd level 1.8v t rrst fedl7344c/e/j-05 ml7344c/e/j 24/154 deep sleep mode characteristics item symbol condition min typ. max unit regpdin assert delay time t rpfd 0 - - s regpdin assert time t rpass 1.2 - - ms resetn release delay time t refd vddio = ?h? 0.5 - - ms power-on characteristics item symbol condition min typ. max unit power on time t pwon power on state (all power supply pins) - - 5 ms vdd vdd level gnd level t pwon 80% 20% vdd level gnd level vddio resetn regpdin t rpfd t refd t rpass fedl7344c/e/j-05 ml7344c/e/j 25/154 function description host interface ser ial peripheral interface (spi) ml7344 has a spi, which supports slave mode. host mcu can read/write to the ml7344 registers and on-chip fifo using mcu clock. single access and burst access are also supported. [single access mode timing chart] in write operation, data will be stored into internal register at rising edge of clock which is capturing d0 data. during write operation, if setting scen line to ?h?, the data will not be stored into register. for more details of scen negate timing, please refer to the ?spi interface characteristics?. afetr the internal clock is stabilized, data will be written into the register in syncrohonization with the internal clock. [write] [read] scen sdi sclk address field r sdo data read field d 7 d 0 a 6 a 0 ?0? scen sdi sclk w write data field address field a 6 a 0 d 7 d 0 ?1? ( register write timing) before clock stable a fter clock stable d7 - 0 d7 - 0 up to 0.45 s fedl7344c/e/j-05 ml7344c/e/j 26/154 [burst access mode timing chart] by maintaining scen line as ?l?, burst access mode will be active. by setting scen line to ?h?, exiting from the burst access mode. during burst access mode, address will be automatically incremented. when scen line becomes ?h? before clock for d0 is input, data transaction will be aborted. note: if destination is [wr_tx_fifo:b0 0x7c] or [rd_fifo:b0 0x7f], address will not be increment. and continuous fifo access is possible. [write] scen write data field a ddress field w write data field a 6 a 0 d 7 d 0 ( register write timing) before clock stable a fter clock stable d7 - 0 d7 - 0 d7 - 0 d7 - 0 ?1? read data field scen a ddress field r read data field [read] a 6 a 0 d 7 d 0 sdo sdi sclk ?0? up to 0.45s up to 0.45s sclk sdi fedl7344c/e/j-05 ml7344c/e/j 27/154 lsi state transition control lsi state transition instruction state can be controlled from mcu by setting registers below. state transition command instruction tx_on set_trx([rf_status:b0 0x0b(3-0)])=0b1001 rx_on set_trx([rf_status:b0 0x0b(3-0)])=0b0110 trx_off set_trx([rf_status:b0 0x0b(3-0)])=0b1000 force_trx_off set_trx([rf_status:b0 0x0b(3-0)])=0b0011 sleep_en sleep_en([sleep/wu _set:b0 0x2d(0)])=0b1 vco_cal_en vco_cal_start([vco_cal_start:b0 0x6f(0)])=0b1 state can be changed without command from mcu. if one of the following condition is met, state is changed automatically according to the following table. in order to enable these functions, the following registers must be programmed. function control bit name automatic tx_on after fifo write completion (auto_tx ) auto_tx_en([rf_status_ctrl:b0 0x0a(4)]) automatic tx_on during fifo write (fast_tx) fast_tx_en([rf_status_ctrl:b0 0x0a(5)]) rf state setting after packet transmission completion txdone_mode[1:0]([rf_status_ctrl:b0 0x0a(1-0)]) rf state setting after packet reception completion rxdone_mode[1:0]([rf_status_ctrl:b0 0x0a(3-2)]) automatic rx_on/tx_on by wake-up timer wakeup_mode([sleep/wu_set:b0 0x2d(6)]) wakeup_en([sleep/wu_set:b0 0x2d(4)]) automatic vco calibration after exit from sleep auto_vcocal_en([vco_cal_start:b0 0x6f(4)]) automatic sleep by timer wu_duration_en([sleep/wu_set:b0 0x2d(5)]) automatic sleep by high speed carrier checking mode fast_det_mode_en([cca_ctrl:b0 0x39(3)]) force_trx_off after pll unlock detection during tx pll_ld_en([pll_lock_detect:b1 0x0b(7)]) fedl7344c/e/j-05 ml7344c/e/j 28/154 state diagram each state transition control is described in the following state diagram. fig.3 lsi state diagram tx_on trx_off force_trx_off sleep tx completion (trx_off) tx start trx_off force_trx_off sleep rx_on vco_cal completion start vco_cal rx completion (trx_off) rx start (syncword detection) rx_on tx_on rx_on start vco_cal trx_off force_trx_off vco_cal completion sleep exit from sleep sleep exit from deep sleep deep sleep [state] deep sleep : deep sleep sleep : sleep trx_off/idle : idle (tx-rx stand-by) pll_wait : pll stand-by tx_on : tx ready (tx data waiting) transmit : tx on-going rx_on : rx stand-by (rx data waiting) receive : rx on-going vco_cal : vco calibration normal sequence (state transition) command from higher layer state ml7344 self controlled state transition state transition instruction pins control trasmit receive rx_on trx_off force_trx_off sleep tx_on pllwait trx_off force_trx_off sleep rx_on tx_on force_trx_off sleep trx_off force_trx_off sleep tx_on force_trx_off sleep trx_off force_trx_off sleep v cocal sleep exit from sleep trx_off idle deep sleep exit from deep sleep tx_on rx_on vco_cal sleep fedl7344c/e/j-05 ml7344c/e/j 29/154 sleep setting deep sleep mode: powers for all blocks except for io pins are turned off. sleep mode: main regulator and 26mhz oscillation circuits are turned off. but sub-regulator is turned-on. the following registers can be programmed to control sleep state function control bit name power control pdn_en([sleep?wu_set:b0 0x2d(1)]) wake-up setting wakeup_en([sleep/wu_set:b0 0x2d(4)]) wake-up timer clock source setting wut_clk_source([sleep/wu_set:b0 0x2d(2)]) internal rc oscillator control rc32k_en([clk_set2:b0 0x03(3)]) setting method and internal state for deep_sleep and various sleep modes are as follows: sleep mode setting method main regulator sub regulator 26mhz oscillator rc oscilator low clock timer fifo deep_sleep resetn pin=?l? regpdin pin=?h? off off off off off off sleep1 [sleep/wu_set: b0 0x2d(4-0)] = 0b0_1011 (*2) [clk_set2: b0 0x03(3)] = 0b0 (default) off on off off off off sleep2 [sleep/wu_set: b0 0x2d(4-0)] = 0b0_1001 (*2) [clk_set2: b0 0x03(3)] = 0b0 (default) off on off off (*1) off on sleep3 [sleep/wu_set: b0 0x2d(4-0)] = 0b1_1001 (*2) [clk_set2: b0 0x03(3)] = 0b0 (default) off on off off on on sleep4 [sleep/wu_set: b0 0x2d(4-0)] = 0b1_1101 (*2) [clk_set2: b0 0x03(3)] = 0b1 off on off on on on (*1) low speed clock is supplied from ext_clk pin. (*2) please set proper value to [sleep/wu_set: b0 0x2d(3)]. note: contents of registers are not kept during deep_sleep. contents of registers are kept during sleep1, sleep2, sleep3 and sleep4. however, in sleep1 mode, contents of tx fifo and rx fifo are not kept, because power to fifo is turned off. fedl7344c/e/j-05 ml7344c/e/j 30/154 notes to set rf state ml7344 is able to change the internal rf state transition autonomously (without commands from mcu) as well as rf state change commands from mcu. (please refer to ?lsi state transition instruction?). if both timing of operation (autonomous state and state change from mcu command) overlapped, unintentional rf state may occur. timing of autonomous state rf change is described in the following table. care must be taken not to overlap the conditions. function rf state change (before after) rf state transition timing (not from host mcu command) recommended process automatic tx after tx data transfer completion interrupt occurs, {value [tx_rate_h/l: b1 0x02/03)] 2 / 26}[ s] period fast_tx mode trx_off/rx_on : tx_on when fifo write access exceed trigger level +1, {value [rx_rate1_h/l:b1 0x04/05] 5 / 26}[ s] period. tx_on : trx_off tx_on : rx_on rf state setting after tx completion tx_on : sleep after tx completion interrupt (int[16] group3), {value [tx_rate_h/l:b1 0x02/03] 2 / 26} [ s] period rx_on : trx_off rx_on : tx_on rf state setting after rx completion rx_on : sleep after rx completion interrupt (int[8] group2), {value [rx_rate1_h/l:b1 0x04/05] 2 / 26}[ s] period sleep : tx_on sleep : rx_on after wake-up timer completion interrupt (int[6] group1), 1 clock cycle period defined by wut_clk_set[3:0] ([wut_clk_set: b0 0x2e(3-0)]). write access to [rf_status:b0 0x0b] is possible after rf state transition completion interrupt (int[3] group1), or move to the state defined by get_trx ([rf_status:b0 0x0b(7-4)]). sleep : vco_cal : tx_on wake-up timer sleep : vco_cal : rx_on after wake-up timer completion interrupt (int[6] group1), before vco calibration completion interrupt (int[1] group1). write access to [rf_status:b0 0x0b] and bank2 is possible after vco calibration completion interrupt (int[1] group1). tx_on : sleep continuous operation timer rx_on : sleep after continuous operation timer completion, 1 clock cycle period defined by wut_clk_set [3:0] ([wut_clk_set: b0 0x2e(3-0)]). high speed carrier checking rx_on : sleep after cca completion interrupt (int[18] group3), duration 6.3[ s]. write access to [rf_status:b0 0x0b] is possible after rf state transition completion interrupt (int[3] group1), or move to the state defined by get_trx ([rf_status:b0 0x0b(7-4)]). pll unlock detection tx_on : trx_off after pll unlock detection interrupt (int[2] group1) occurs, duration 147[ s]. write access to [rf_status:b0 0x0b] is possible 147 s after pll unlock interrupt (int[2] group1) detected. fedl7344c/e/j-05 ml7344c/e/j 31/154 packet handling function pack et format ml7344 supports wireless m-bus frame formata/b, and format c which is non wireless m-bus universal format. the following packet handling are supported in fifo mode or dio mode 1) preamble and syncword automatic insertion (tx) --- dio/fifo mode 2) preamble and syncword automatic detection (rx) --- dio/fifomode 3) preamble and syncword automatic deletion (rx) --- dio/fifo mode 4) crc data insertion (tx) --- fifo mode 5) crc check and error notification (rx) --- dio/fifo mode the following table shows the control bit relating with packet format function. function control bit name packet format setting pkt_format[1:0] ([pkt_ctrl1: b0 0x04(1-0)]) rx extended link layer mode disable rx_extpkt_off ([pkt_ctrl1: b0 0x04(3)]) data area bit order setting dat_lf_en ([pkt_ctrl1: b0 0x04(4)]) length area bit order setting len_lf_en ([pkt_ctrl1: b0 0x04(5)]) extended link layer mode setting ext_pkt_mode[1:0] ([pkt_ctrl1: b0 0x04(7-6)]) length field setting length_mode ([pkt_ctrl2: b0 0x05(0)]) fedl7344c/e/j-05 ml7344c/e/j 32/154 (1) format a (wireless m-bus) by setting pkt_format[1:0] ([pkt_ctrl1: b0 0x04(1- 0)])=0b00, wireless m-bus format a is selected. format a consists of 1 st block, 2 nd block and optional block(s). each block has 2 bytes of crc. ?l-field? (1 st byte of 1 st block) indicates packet length, which includes subsequenct user data bytes from ?c-field?. however, crc bytes and postanble are excluded. depending on ?l-field? value, 2 nd block and optional block(s) are added. the following [] indicates register address [bank #, address]. *1: each mode has different minimum value of n. *2: indicates tx fifo data storage area size. *3: indicates rx fifo data storage area size. *4: when rxdio_ctrl[1:0] ([dio_set: b0 0x0c(7-6)])=0b10, indicates dclk/dio output area. (*2) length msb lsb preamble sync word tx: automatic insertion rx: automatic detection, deletion manchester/3-out-of-6 applicable [b0 0x07(3-2, 1-0)] 1st block 2nd block o p tional block postamble l field 1 byte c field 1 byte m field 2 bytes a field 6 bytes crc field 2 bytes ci field 1 byte crc field 2 bytes crc field 2 bytes data field max.15 bytes data field max.16 bytes 0/2-8 bits 10/18/ 32bits > n*2(*1) bits crc applicable crc applicable crc applicable (*2) (*2) (*3) (*4) [b0 0x07] [b0 0x42] [b0 0x43] [b0 0x08] [b1 0x25-2e] [b0 0x05] [b0 0x7a/7b, 7d/7e] [b0 0x44] fedl7344c/e/j-05 ml7344c/e/j 33/154 extended link layer format if ?ci-field? (1 st byte of 2 nd block)=0x8c or 0x8d, extended link layer is applied. the packet format is as follows: (1) ci-field = 0x8c for tx, if 2 bytes extention format is used, set ext_pkt_mode[1:0] ([pkt_ctrl1: b0 0x04(7-6)])=0b01. for rx, if rx_extpkt_off([pkt_ctrl1: b0 0x04(3)])=0b0, ml7344 recognizes ?ci-field? and rx operation is processed. *1: 1 st block is identical to normal format a. *2: indicates tx fifo data storage area size. *3: indicates rx fifo data storage area size. *4: when rxdio_ctrl[1:0] ([dio_set: b0 0x0c(7-6)])=0b10, indicates dclk/dio output area. length msb lsb preamble sync word tx: automatic insertion rx: automatic detection, deletion manchester/3-out-of-6 applicable [b0 0x07(3-2,1-0)] 1st block (*1) 2nd block o p tional block postamble l field 1 byte c to crc field 11 bytes ci field 1 byte acc field 1 byte ci field 1 byte crc field 2 bytes crc field 2 bytes data field max.12 bytes data field max.16 bytes 0/2-8 bits 10/18/ 32bits > n*2(*1) bits crc applicable crc applicable (*2) (*2) (*3) (*4) [b0 0x07] [b0 0x42] [b0 0x43] [b0 0x08] [b1 0x25-2e] [b0 0x05] [b0 0x7a/7b, 7d/7e] [b0 0x44] cc field 1 byte extended block fedl7344c/e/j-05 ml7344c/e/j 34/154 (2) ci-field = 0x8d for tx, if 8 bytes extention format is used, set ext_pkt_mode[1:0] ([pkt_ctrl1: b0 0x04(7-6)])=0b10. for rx, if rx_extpkt_off([pkt_ctrl1: b0 0x04(3)])=0b0, ml7344 recognizes ?ci-field? and rx operation is processed. *1: 1 st block is identical to normal format a. *2: indicates tx fifo data storage area size. *3: indicates rx fifo data storage area size. *4: when rxdio_ctrl[1:0] ([dio_set: b0 0x0c(7-6)])=0b10, indicates dclk/dio output area. length msb lsb preamble sync word tx: automatic insertion rx: automatic detection, deletion manchester/3-out-of-6 applicable [b0 0x07(3-2,1-0)] 1st block (*1) 2nd block optional block postamble l field 1 byte c - crc field 11 bytes ci field 1 byte acc field 1 byte ci field 1 byte crc field 2 bytes crc field 2 bytes data field max.15 bytes data field max.16 bytes 0/2-8 bits 10/18/ 32bits > n*2(*1) bits crc applicable crc applicable (*2) (*2) (*3) (*4) [b0 0x07] [b0 0x42] [b0 0x43] [b0 0x08] [b1 0x25-2e] [b0 0x05] [b0 0x7a/7b, 7d/7e] [b0 0x44] cc field 1 byte extended block crc field 2 bytes (*2) crc applicable sn field 4 bytes fedl7344c/e/j-05 ml7344c/e/j 35/154 (2) format b (wireless m-bus) by setting pkt_format[1:0] ([pkt_ctrl1: b0 0x04(1- 0)])=0b00, wireless m-bus format b is selected. format b consists of 1 st block, 2 nd block and optional block(s). each block has 2 bytes of crc. ?l-field? (1 st byte of 1 st block) indicates packet length, which includes subsequenct user data bytes from ?c-field?. however, unlike format a, crc bytes are included. (postanble are excluded.) depending on ?l-field? value, 2 nd block and optional block(s) are added. the following [] indicates register address [bank #, address]. *1: each mode has different minimum value of n. *2: indicates tx fifo data storage area size. *3: indicates rx fifo data storage area size. *4: when rxdio_ctrl[1:0] ([dio_set: b0 0x0c(7-6)])=0b10, indicates dclk/dio output area. length msb lsb preamble sync word tx: automatic insertion rx: automatic detection, deletion manchester/3-out-of-6 applicable [b0 0x07(3-2,1-0)] 1st block 2nd block optional block postamble l field 1 byte c field 1 byte m field 2 bytes a field 6 bytes ci field 1 byte crc field 2 bytes crc field 2 bytes data field max.115 bytes data field max.126 bytes 0/2-8 bits 10/18/ 32bits > n*2(*1) bits crc applicable crc applicable (*2) (*2) (*3) (*4) [b0 0x07] [b0 0x42] [b0 0x43] [b0 0x08] [b1 0x25-2e] [b0 0x05] [b0 0x7a/7b, 7d/7e] [b0 0x44] fedl7344c/e/j-05 ml7344c/e/j 36/154 extended link layer format if ?ci-field? (1 st byte of 2 nd block)=0x8c or 0x8d, extended link layer is applied. the packet format is as follows: (1) ci-field = 0x8c for tx, if 2 bytes extention format is used, set ext_pkt_mode[1:0] ([pkt_ctrl1: b0 0x04(7-6)])=0b01. for rx, if rx_extpkt_off([pkt_ctrl1: b0 0x04(3)])=0b0, ml7344 recognizes ?ci-field? and rx operation is processed. *1: 1 st block is identical to normal format b. *2: indicates tx fifo data storage area size. *3: indicates rx fifo data storage area size. *4: when rxdio_ctrl[1:0] ([dio_set: b0 0x0c(7-6)])=0b10, indicates dclk/dio output area. length msb lsb preamble sync word tx: automatic insertion rx: automatic detection, deletion 1st block (*1) 2nd block o p tional block postamble l field 1 byte c, m, a field 9 bytes ci field 1 byte acc field 1 byte ci field 1 byte crc field 2 bytes crc field 2 bytes data field max.112 bytes data field max.126 bytes 0/2-8 bits 10/18/ 32bits > n*2(*1) bits crc applicable crc applicable (*2) (*2) (*3) (*4) [b0 0x07] [b0 0x42] [b0 0x43] [b0 0x08] [b1 0x25-2e] [b0 0x05] [b0 0x7a/7b, 7d/7e] [b0 0x44] cc field 1 byte extended block manchester/3-out-of-6 applicable [b0 0x07(3-2,1-0)] fedl7344c/e/j-05 ml7344c/e/j 37/154 (2) ci-field = 0x8d for tx, if 8 bytes extention format is used, set ext_pkt_mode[1:0] ([pkt_ctrl1: b0 0x04(7-6)])=0b10. for rx, if rx_extpkt_off([pkt_ctrl1: b0 0x04(3)])=0b0, ml7344 recognizes ?ci-field? and rx operation is processed. *1: 1 st block is identical to normal format b. *2: indicates tx fifo data storage area size. *3: indicates rx fifo data storage area size. *4: when rxdio_ctrl[1:0] ([dio_set: b0 0x0c(7-6)])=0b10, indicates dclk/dio output area. length msb lsb preamble sync word tx: automatic insertion rx: automatic detection, deletion manchester/3-out-of-6 applicable [b0 0x07(3-2,1-0)] 1st block (*1) 2nd block optional block postamble l field 1 byte c,m,a field 9 bytes ci field 1 byte acc field 1 byte ci field 1 byte crc field 2 bytes crc field 2 bytes data field max.106 bytes data field max.126 bytes 0/2-8 bits 10/18/ 32bits > n*2(*1) bits crc applicable crc applicable (*2) (*2) (*3) (*4) [b0 0x07] [b0 0x42] [b0 0x43] [b0 0x08] [b1 0x25-2e] [b0 0x05] [b0 0x7a/7b, 7d/7e] [b0 0x44] cc field 1 byte extended block crc field 2 bytes (*2) crc applicable sn field 4 bytes fedl7344c/e/j-05 ml7344c/e/j 38/154 (3) format c (non wireless m-bus, general purpose format) by setting pkt_format([pkt_ctrl1: b0 0x04(1-0)])=0b10, format c, which is non wireless m-bus format, is selected. format c consists of 1 st block only, which has 2 bytes of crc. ?l-field? indicates packet length, which includes subsequent user data bytes, including crc bytes. the length of ?l-field? is defined by length_mode ([pkt_ctrl2:b0 0x5(0]). data whitening function is supported. the following [] indicates register address [bank #, address]. *1: preamble length (n) is programable by [txpr_len_h/l: b0 0x42/43] registers. *2: indicates tx fifo data storage area size. *3: indicates rx fifo data storage area size. *4: when rxdio_ctrl[1:0] ([dio_set: b0 0x0c(7-6)])=0b10, indicates dclk/dio output area. length msb lsb preamble sync word tx: automatic insertion rx: automatic detection, deletion manchester/3-out-of-6 applicable [b0 0x07(3-2,1-0)] 1st block postamble l field 1/2 byte crc field 0/1/2/4 bytes data field max.2047 bytes 0/2-8 bits max. 32bits > n*2(*1) bits crc applicable (*2) (*3) (*4) [b0 0x07] [b0 0x42] [b0 0x43] [b0 0x08] [b1 0x25-2e] [b0 0x05] [b0 0x7a/7b] [b0 0x7d/7e] [b0 0x44] whitening applicable [b0 0x08(0)] [b0 0x05] fedl7344c/e/j-05 ml7344c/e/j 39/154 crc function ml7344 has crc32,crc16 and crc8 function. crc is calculated and appended to tx data. crc is checked for rx data. the following modes are used for automatic crc function. fifo mode: rxdio_ctrl ([dio_set: b0 0x0c(7-6)]) = 0b00 dio mode: rxdio_ctrl ([dio_set: b0 0x0c(7-6)]) = 0b11 function control bit name / register tx crc setting tx_crc_en([pkt_ctrl2: b0 0x05(2)]) rx crc setting rx_crc_en([pkt_ctrl2: b0 0x05(3)]) crc length setting crc_len([pkt_ctrl2: b0 0x05(5-4)]) crc complement value off setting crc_comp_off([pkt_ctrl2: b0 0x05(6)]) crc polynomial setting [crc_poly3/2/1/0: b1 0x16/17/18/19] registers crc error status [crc_err_h/m/l: b0 0x13/14/15] registers any crc polynomials for crc32/crc16/crc8 can be specified. reset value is as follows: crc16 polynomial = x 16 + x 13 + x 12 + x 11 + x 10 + x 8 + x 6 + x 5 + x 2 + 1 (reset value) note: crc result data can be inverted by crc complement value off setting, crc data will be generated by the following circuits. by programming [crc_poly3/2/1/0] registers, any crc polynomials can be supported. generated crc will be transfer from the most left bit (s15). if data length is shorter than crc length (3 bytes of crc32 only), data ?0?s will be added for crc calculation. crc check result is stored in [crc_err_h/m/l] registers. unlike format c, format a/b can include multiple crc fields in one packet. for multiple crcs check results, crc value closest to l-field will be stored in crc_err[0] ([crc_err_l:b0 0x15(0)]). subsequent bit will be stored in crc_err from msb order. note: exclusive or fig.4 crc16 polynomial circuits general crc polynomial can be programmed by below [crc_poly3/2/1/0] register setting. crc length can be set by crc_len. [crc_poly3/2/1/0] crc polynomial (b1 0x16) (b1 0x17) (b1 0x18) (b1 0x19) crc8 x 8 + x 2 + x + 1 0x00 0x00 0x00 0x03 x 16 + x 12 + x 5 + 1 0x00 0x00 0x08 0x10 x 16 + x 15 + x 2 + 1 0x00 0x00 0x40 0x02 crc16 x 16 + x 13 + x 12 + x 11 + x 10 + x 8 + x 6 + x 5 + x 2 + 1 0x00 0x00 0x1e 0xb2 crc32 x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1 0x02 0x60 0x8e 0xdb s0 s1 s2 s14 s15 crc_poly [14] crc_poly [0] crc_poly [1] crc_poly [13] input data fedl7344c/e/j-05 ml7344c/e/j 40/154 data whitening function (non wireless m-bus standard) ml7344 supports data whitening function. in packet format a/b, subsequent data followed by c-field can be processed data whitening. in packet format c, data whitening is applied from data field. data generated by the following 9 bit pseudo random sequence (pn9) will be ?xor? with tx data (encoded data if manchester or 3-out-of 6 coding is selected) before transmission. intialization value of the pn9 generation shift register can be defined by [wht_init_h/l: b1 0x64/65] registers. pn9 polynomial can be programmed with [wht_cfg: b1 0x66] register. function control bit name data whitening setting enable wht_set ([data_set2: b0 0x08(0)]) data whitening initialization value wht_init [8:0] ([wht_init_h/l: b1 0x64(0)/65(7-0)]) whitening polynomial wht_cfg[7:0] ([wht_cfg: b1 0x66(7-0)]) in order to make feedback from s1 register, setting 0b1 to wht_cfg0 ([wht_cfg: b1 0x66(0)]). similaly in order to make feedback from s2 register, setting 0b1 to wht_cfg1 ([wht_cfg: b1 0x66(1)]). other bits of [wht_cfg: b1 0x66] register has same function. two or more bits can be also set to 0b1. therefore any type of pn9 polinominal can be programmed. note: exclusive or fig.5 whitening data generation circuits (generator polynomial: x 9 + x 5 + 1) general pn9 polynomial can be defined by wht_cfg[7:0]. pn9 polynomial wht_cfg[7:0] [wht_cfg: b1 0x66] x 9 + x 4 + 1 0x08 x 9 + x 5 + 1 0x10 s8 s7 s6 s5 s4 s3 s2 s1 s0 whitening data fedl7344c/e/j-05 ml7344c/e/j 41/154 syncword detection function ml7344 supports automatic syncword recognition function. by having two sets of syncword pattern storage area, it is possible to detect two different packet format (format a/b) which are defined by wireless m-bus. (for details, please refer to wireless m-bus standa rd) receiving packet format is indicated by sw_det_rslt([stm_state:b0 0x77(5)]). in format c, it is possible to search for two syncwords but detected result is not indicated. 1) tx syncword pattern defined by syncword_sel ([data_set2: b0 0x08(4)]) will be selected. syncword length for tx is defined by sync_word_len[5:0] ([sync_word_len: b1 0x25(5-0)]). from high bit of each syncword pattern will be transmitted. syncword_sel tx syncword pattern 0 sync_word1[31:0] ([syncword1_set3/2/1/0: b1 0x27/28/29/2a]) 1 sync_word2[31:0] ([syncword2_set3/2/1/0: b1 0x2b/2c/2d/2e]) [example] syncword patten and syncword length if the follwing registers are programmed, from higher bit of sync_word1[17:0] will be transmitted sequencially. [sync_word_len: b1 0x25]=0x12 syncword_sel ([data_set2: b0 0x08(4)]) = 0b0 if the following registers are programmed, from hi gher bit of sync_word2[23:0] will be transmitted sequencially. [sync_word_len: b1 0x25]=0x18 syncword_sel ([data_set2: b0 0x08(4)]) = 0b1 2) rx by setting syncword_sel and 2sw_det_en ([data_set2: b0 0x08(4,3)]), one syncword pattern waiting or two syncword patterns waiting can be selected as follows: packet format automatic detection is valid if 2sw_det_en=0b1 and format a or fromat b is selected by pkt_format[1:0] ([pkt_ctrl1:b0 0x04(1-0)]). 2sw_ det_en syncword _sel syncword pattern during sync detection syncword detection operation automatic packet format detection data process after syncword 0 0 sync_word1[31:0] waiting for 1 pattern no process according to each format setting 0 1 sync_word2[31:0] waiting for 1 pattern no process according to each format setting 1 ? sync_word1[31:0] sync_word2[31:0] waiting for 2 patterns yes [format a or format b setting] if matched with sync_word1, then process as format a. if matched with sync_word2, then process as format b. [format c setting] process as format c fedl7344c/e/j-05 ml7344c/e/j 42/154 length of syncword pattern can be defined by sync_word_len[5:0] ([sync_word_len: b1 0x25(5-0)]). in this case, syncword pattern defined by the length from low bit of sync_word1[31:0] or sync_word2[31:0] will be the pattern for checking. [example] syncword length if the following registers are set, 18 bit of sync_word1[17:0] or sync_word2[17:0] will be reference pattern for the syncword detection. higher bits (bit31-18) are not checked. [sync_word_len: b1 0x25]=0x12 [sync_word_en: b1 0x26]=0x0f 32bit syncword pattern can be controlled by enabling /disabling by each 8bit, when receiving syncword. the following table describes enable/disable control and syncword pattern. sync_word* [sync_word_en] (b1 0x26) [31:24] [23:16] [15:8] [7:0] syncword detection operation 0000 no syncword detection 0001 d.c.(*1) on only [7:0] are valid. upon [7:0] detection, syncword detection. 0010 d.c. on d.c. only [15:8] are valid. upon [7:0] detection, syncword detection. 0011 d.c. on on [15:0] are valid. upon [7:0] detection, syncword detection. 0100 d.c. on d.c. only [23:16] are valid. upon [7:0] detection, syncword detection. 0101 d.c. on d.c. on [23:16] and [7:0] are valid. upon [7:0] detection, syncword detection. 0110 d.c. on on d.c. [23:8] are valid. upon [7:0] detection, syncword detection. 0111 d.c. on on on [23:0] are valid. upon [7:0] detection, syncword detection. 1000 on d.c. only [31:24] are valid. upon [7:0] detection, syncword detection. 1001 on d.c. on [31:24] and [7:0] are valid. upon [7:0] detection, syncword detection. 1010 on d.c. on d.c. [31:24] and [15:8] are valid. upon [7:0] detection, syncword detection. 1011 on d.c. on on [31:24] and [15:0] are valid. upon [7:0] detection, syncword detection. 1100 on on d.c. [31:16] are valid. upon [7:0] detection, syncword detection. 1101 on on d.c. on [31:16] and [7:0] are valid. upon [7:0] detection, syncword detection. 1110 on on on d.c. [31:8] are valid. upon [7:0] detection, syncword detection. 1111 on on on on whole [31:0] are valid. upon [7:0] detection, syncword detection. (*1) d.c. stands for don?t care. (*2) preamble pattern can be added to the syncword detection conditions by rxpr_len[5:0] ([sync_condition1 :b0 0x45(5-0)]). fedl7344c/e/j-05 ml7344c/e/j 43/154 field check function ml7344 has the function of comparing the 9 bytes following l-field (format a/b: start from c-field, format c: start from data-field) in a receiving packet. base d on comparison with the expected data, possible to generate interrupts (field check function). field check can be possible with the following register setting. when using this function, rxdio_ctrl [1:0] ([dio_set:b0 0x0c(7-6)]) = 0b00 (fifo mode) or 0b11 (data output mode 2) setting is required. function register rx data process setting when field check unmatched [c_check_ctrl: b0 0x1b(7)] field check interrupt setting [c_check_ctrl: b0 0x1b(6)] c-field detection enable setting [c_check_ctrl: b0 0x1b(4-0)] m-field detection enable setting [m_check_ctrl: b0 0x1c(3-0)] a-field detection enable setting [a_check_ctrl: b0 0x1d(5-0)] c-field code setting [c_field_code1: b0 0x1e] [c_field_code2: b0 0x1f] [c_field_code3: b0 0x20] [c_field_code4: b0 0x21] [c_field_code5: b0 0x22] m-field code setting [m_field_code1: b0 0x23] [m_field_code2: b0 0x24] [m_field_code3: b0 0x25] [m_field_code4: b0 0x26] a-field code setting [a_field_code1: b0 0x27] [a_field_code2: b0 0x28] [a_field_code3: b0 0x29] [a_field_code4: b0 0x2a] [a_field_code5: b0 0x2b] [a_field_code6: b0 0x2c] the following describes the relation between each comparison code and incoming rx data. [format a/b(wireless m-bus)] field check can be controlled by setting disabled/enabled for each comparison code (1 byte). if all specified field data (c-field/m-field/a-field) are matched, field checking matching will be notified. however, if c-field data and c_field_code5 are matched, even if other fiel d data (m-field/a-field) are not matched, field check result will be notified as ?match?. msb preamble sync word l field 1st block a field c field m field 1 byte 1 byte 2 bytes 10/18/ 32bits over n*2 bit 6 bytes crc field 0/2 bytes c1: [c_field_code1: b0 0x1e] c2: [c_field_code2: b0 0x1f] c3: [c_field_code3: b0 0x20] c4: [c_field_code4: b0 0x21] c5: [c_field_code5: b0 0x22] a1. [a_field_code1: b0 0x27] a2. [a_field_code2: b0 0x28] a3. [a_field_code3: b0 0x29] a4. [a_field_code4: b0 0x2a] a5. [a_field_code5: b0 0x2b] a6. [a_field_code6: b0 0x2c] a1 a2 a3 a4 a5 a6 lsb m1. [m_field_code1: b0 0x23] m2. [m_field_code2: b0 0x24] m3. [m_field_code3: b0 0x25] m4. [m_field_code4: b0 0x26] m1 m2 m3 m4 c1 c2 c3 c4 c5 fedl7344c/e/j-05 ml7344c/e/j 44/154 check field comparison code conditions for match c-field c_field_code1 or c_field_code2 or c_field_code3 or c_field_code4 or c_field_code5 if one of the 5 comparison code is matched m-field 1 st byte m_field_code1 or m_field_code2 if one of the 2 comparison code is matched. m-field 2 nd byte m_field_code3 or m_field_code4 if one of the 2 reference pattern is matched. a-field a_field_code1/2/3/4/5/6 if comparison codes are matched. [format c] field check can be controlled by setting disabled/enabled for each comarison code (1 byte). if all specified field data (specified table below) are matched, field checking matching will be notified. however, if 1 st byte of data field and c_field_code5 are matched, even if other field data(from 2 nd byte to 9 th byte) are not matched, field check result will be notified as ?match?. check field comparison code conditions for match data-field 1 st byte c_field_code1 or c_field_code2 or c_field_code3 or c_field_code4 or c_field_code5 if one of the 5 comparison code is matched data-field 2 nd byte m_field_code1 or m_field_code2 if one of the 2 comparison code is matched. data-field 3 rd byte m_field_code3 or m_field_code4 if one of the 2 comparison code is matched. data-field 4 th byte a_field_code1 if comparison code is matched. data-field 5 th byte a_field_code2 if comparison code is matched. data-field 6 th byte a_field_code3 if comparison code is matched. data-field 7 th byte a_field_code4 if comparison code is matched. data-field 8 th byte a_field_code5 if comparison code is matched. data-field 9 th byte a_field_code6 if comparison code is matched. msb preamble sync word l field 1st block data field 1 byte 1 byte 10/18/ 32bits over n*2 bit 1 byte a1 a2 a3 a4 a5 a6 lsb m1 m2 m3 m4 c1 c2 c3 c4 c5 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte c1: [c_field_code1: b0 0x1e] c2: [c_field_code2: b0 0x1f] c3: [c_field_code3: b0 0x20] c4: [c_field_code4: b0 0x21] c5: [c_field_code5: b0 0x22] a1. [a_field_code1: b0 0x27] a2. [a_field_code2: b0 0x28] a3. [a_field_code3: b0 0x29] a4. [a_field_code4: b0 0x2a] a5. [a_field_code5: b0 0x2b] a6. [a_field_code6: b0 0x2c] m1. [m_field_code1: b0 0x23] m2. [m_field_code2: b0 0x24] m3. [m_field_code3: b0 0x25] m4. [m_field_code4: b0 0x26] fedl7344c/e/j-05 ml7344c/e/j 45/154 packet processing as a result of field checking by setting ca_rxd_clr ([c_check_ctrl: b0 0x1b(7)])=0b1, if the result of field check is unmatch, data packet will be aborted and wait for next packet data. storing number of unmatched packets unmatched packets can be counted up to max. 2047 packets and result are stored in [addr_chk_ctr_h: b1 0x62] and[addr_chk_ctr_l: b1 0x63]. this count value can be cleared by state_clr4 ([state_clr: b0 0x16(4)]). fedl7344c/e/j-05 ml7344c/e/j 46/154 fifo control function ml7344 has on-chip tx_fifo(64byte) and rx_fifo(64byte). as tx/rx_fifo do not support multiple packets, packet should be processed one by one. if rx _fifo keeps rx packet and next rx packet is received, rx_fifo will be overwritten. it applies to tx_fifo as well. however tx fifo access error interrupt (int[20] group3) will be generated. when receiving, rx data is stored in fifo (byte by byte) and the host mcu will read rx data through spi. when transmitti ng, host mcu write tx data to tx_fifo through spi and transmitting through rf. writing or reading to fifo is through spi with burst access. tx data is written to [wr_tx_fifo: b0 0x7c] register. rx data is read from [rd_fifo: b0 0x7f] register. continuous access increments internal fifo counter automatically. if fifo access is suspended during write or read operation, address will be kept until the packet will be process again. therefore, when resuming fifo access, next data will be resumed from the suspended address. fifo control register are as follows: function register tx fifo full level setting [txfifo_thrh: b0 0x17] tx fifo empty level setting [txfifo_thrl: b0 0x18] rx fifo full level setting [rxfifo_thrh: b0 0x19] rx fifo empty level setting [rxfifo_thrl: b0 0x1a] fifo readout setting [fifo_set: b0 0x78] rx fifo data usage status indication [rx_fifo_last: b0 0x79] tx packet length setting [tx_pkt_len_h/l: b0 0x7a/7b] rx packet length setting [rx_pkt_len_h/l: b0 0x7d/7e] tx fifo [wr_tx_fifo: b0 0x7c] fifo read [rd_fifo: b0 0x7f] [tx] i) tx data l-field value is set to [tx_pkt_len_h: b0 0x7a], [tx_pkt_len_l: b0 0x7b] register. if length is 1 byte, [tx_pkt_len_l] register will be transmitted. length can be set to length_mode([pkt_ctrl2: b0 0x05(0)]). ii) tx data is written to [wr_tx_fifo:b0 0x7c] register. note: 1. if tx_fifo write sequence is aborted during transmission, state_clr0 [state_clr:b0 0x16(0)] (tx fifo pointer clear) must be issued. otherwise data pointer is kept in the lsi and the next packet is not processed properly. for example, tx fifo access error interrupt (int[20] group3) is generated. this interrupt can be generated when the next packet data is writren to the tx_fifo before transmitting previous packet data or fifo overrun (fifo is written when no tx_fifo sp ace) or underrun (attempt to transmit when tx_fifo is empty) 2. depending on the packet format, tx data length value is different. format a: length includs data area excluding l-field and crc data. format b: length includes data area excluding l-field. format c: length includes data area excluding l-field. fedl7344c/e/j-05 ml7344c/e/j 47/154 [rx] i) l-field (length) is read from [rx_pkt_len_h: b0 0x7d], [rx_pkt_len_l: b0 0x7e] registers. ii) reading rx data from fifo. when reading fr om rx_fifo, set fifo_r_sel([fifo_set: b0 0x78(0)])= 0b0. if fifo_r_sel=0b1 , tx_fifo will be selected. data usage value of rx_fifo is indicated by [rx_fifo_last: b0 0x79] register. note: 1. if reading fifo data is terminated before reading all data, state_clr1 [state_clr: b0 0x16(1)] (rx fifo pointer clear) must be issued. otherwise if rx_fifo is not cleared, the pointer controlling fifo data keeps the same status. next rx data will not be processed in the fifo properly. for example, when rx_fifo access error interrupt (int[ 12] group2) is generated. this interrupt occurs when rx_fifo overrun (data received when no space in rx_fifo) or underrun (reading empty rx_fifo). 2. if 1 packet data is kept in the rx_fifo, next rx data will be overwritten. if tx/rx pack is larger than fifo size, fifo access can be controlled by fifo-full trigger or fifo-empty trigger. (1) tx_fifo usage notification function this function is to notice tx_fifo usage to th e mcu using interrupt (sintn). if tx_fifo usage (un-transmitted data in tx_fifo) exceed the full level threshold set by [txfifo_thrh: b0 0x17] register, interrupt will generate as fifo-full interrupt (int[5] group1). if tx_fifo usage is smaller than empty level threshold set by [txfifo_thrl: b0 0x18] register, fifo-empty interrupt will generate as fifo-empty interrout (int[4] grou1). interrupt signal (sintn ) can be output from gpio* or ext_clk pin. for output setting, please refer to [gpio1_ctrl: b0 0x4e], [gpio1_ctrl: b0 0x4f], [gpio2_ctrl: b0 0x50], [gpio3_ctrl: b0 0x51], [extclk_ctrl: b0 0x52] registers for output setting. empty level (example 0x0f) full level (example 0x2e) 0x3f generate interrupt when tx data usage is smaller than em p t y level [fifo usage] time full level empty level tx data amount tx_fifo usage transition 0x0f 0x2e sintn signal tx data amount tx_fifo usage tx start timing by fast_tx trigger clear interrupt 0x00 generate interrupt when written data exceed full level fedl7344c/e/j-05 ml7344c/e/j 48/154 [reference sequence]: 1. set full level threshold and empy level threshold..each threshold should set as txfifo_thrh[5:0] ([txfifo_thrh:b0 0x17(5-0)]) > txfifo_thrl[5:0] ([txfifo_thrl:b0 0x18(5-0)]). and enabling full level threshold by txfifo_thrh_en([txfifo_thrh:b0 0x17(7)=0b1. 2. enabling fast_tx mode by fast_tx_en([rf_status_ctrl:b0 0x0a(5)])=0b1 and start writing tx data to the tx_fifo[wr_tx_fifo:b0 0x7c] until fifo-full interrupt (int[5] group1) occurs. 3. after fifo-full interrupt is generated, clear the interupt. then disabling full level threshold (txfifo_thrh_en= 0b0) and enabling empty level threshold (txfifo_thrl_en ([txfifo_thrl:b0 0x18(7)])=0b1). 4. after fifo-empty interrupt (int[4] group1) is generated, clear the interupt. then disabling empty level threshold (txfifo_thrl_en=0b0) and enabling full level threshold (txfifo_thrh_ en=0b1). then resume writing tx data to the tx_fifo until next fifo-full interrupt occurs. 5. repeat 3.-4. until completion of tx. note: when skip disabling threshold level at sequece 3. or 4., depending on tx data read (phy block) and tx_fifo write timing through spi, in the middle of tx_fifo writing, unwiilling fifo-full interrupt or fifo-empty interrupt may occurs. fedl7344c/e/j-05 ml7344c/e/j 49/154 (2) rx_fifo usage notification function this function is to notify remaining rx_fifo by using interrupt (sintn) to the mcu. if rx_fifo usage (un-read data in rx_fifo) exceed full level thresh old defined by [rxfifo_thrh: b0 0x19] register, interrupt will generate as fifo-full interrupt (int[5] group1). after mcu read rx data from rx_fifo, un-read amount become smaller than empty level threshold defined by [rxfifo_thrl: b0 0x1a] register, interrupt will generated as fifo-empty (int[4] group1) . interrupt signal (sintn) can be output from gpio* or ext_clk. for output setting, please refer to [gpio1_ctrl: b0 0x4e], [gpio1_ctrl: b0 0x4f], [gpio2_ctrl: b0 0x50], [gpio3_ctrl: b0 0x51], [extclk_ctrl: b0 0x52] registers. [reference sequence]: 1. set full level threshold and empy level threshold..each threshold should set as rxfifo_thrh[5:0] ([rxfifo_thrh:b0 0x19(5-0)]) > rxfifo_thrl[5:0] ([rxfifo_thrl:b0 0x1a(5-0)]). and enabling full level threshold by rxfifo_thrh_en([rxfifo_thrh:b0 0x19(7)=0b1. 2. after issuing rx_on, wait fifo-full interrupt (int[5] group1) generation. 3. after fifo-full interrupt is generated, clear the interupt. then disabling full level threshold (rxfifo_thrh_en= 0b0) and enabling empty level threshold (rxfifo_thrl_en ([rxfifo_thrl:b0 0x1a(7)])=0b1). and start reading rx data from rx_fifo [rd_fifo:b0 0x7f]. 4. after fifo-empty interrupt (int[4] group1) is generated, clear the interupt. then disabling empty level threshold (txfifo_thrl_en=0b0) and enabling full level threshold (txfifo_thrh_ en=0b1). then resume writing tx data to the tx_fifo until next fifo-full interrupt occurs. 5. repeat 3.-4. until completion of rx data read out. note: when skip disabling threshold level at sequece 3. or 4., depending on rx data write (phy block) and rx_fifo read timing through spi, in the middle of rx_fifo reading, unwiilling fifo-full interrupt or fifo-empty interrupt may occurs. empty level (example 0x0f) full level (example 0x2e) 0x3f generate interrupt when un-read data amount is less than empty level after read rx data from rx fifo. [fifo usage] time full level empt y level rx data amount rx_fifo usage transition 0x0f 0x2e sintn signal rx data amount rx fifo usage clear interrupt 0x00 generate interrupt when rx data exceed full level fedl7344c/e/j-05 ml7344c/e/j 50/154 dio function using gpio0-3, ext_clk or sdi/sdo pins, tx/rx data can be input/output. pins can be configured by [gpio*_ctrl: b0 0x4e/0x4f/0x50/0x51], [extclk_ctrl: b0 0x52] and [spi/ext_pa_ctrl: b0 0x53] registers. data format for tx/rx are as follows: tx --- tx data (nrz or manchester/3-out-of-6coding) will be input. rx --- pre-decoded rx data or decoded rx data will be output. (selectable by [dio_set: b0 0x0c] register) dio function registers are as follows: function registers dio rx data output start setting [dio_set: b0 0x0c(0)] dio rx completion setting [dio_set: b0 0x0c(2)] tx dio mode setting [dio_set: b0 0x0c(5-4)] rx dio mode setting [dio_set: b0 0x0c(7-6)] (1)in case of using gpio*, ext_clk pins if gpio0-3 or ext_clk pins are used as dclk/dio, dclk/dio should be controlled as follow. (below dio/dclk vertical line part indicate output or input period) [tx] i) continuous input mode (from host) set txdio_ctrl[1:0] ([dio_set: b0 0x0c(5-4)]) =0b01. after tx_on(set_trx[3:0]([rf_status: b0 0x0b(3-0)])=0x9), dclk is output continuously. at falling edge of dclk, tx data is input from dio pin. tx data must be encoded data. note: for details of timing, please refer to the ?tx? in the ?timing chart?. dio(gpio0-3,ext_clk) tx_on command tx data dclk(gpio0-3,ext_clk) preamble syncword data-field trx_off command tx_on fedl7344c/e/j-05 ml7344c/e/j 51/154 ii) data input mode (from host) set txdio_ctrl[1:0] ([dio_set: b0 0x0c(5-4)]) =0b10. after tx_on, dclk is output during data input period after syncword. tx data is input at falling edge of dclk through dio input. encoded tx data must be transferred from the host. preamble and syncwordis generated automatically according to the registers setting. note:. preamble can be set by pb_pat([data_set1: b0 0x07(7)] and txpr_len[15:0] ([txpr_len_h/l:b0 0x42/43]). syncword can be set by syncword_sel([data_set1: b0 0x08(4)), syncword_len[5:0] ([sync_word_ len: b1 0x25(5-0)]), sync_word_en* ([sync_word_en: b1 0x26(3-0)]), sync_word1[31:0] ([syncword1_ set3/2/1/0: b1 0x27/28/29/2a]) and sync_word2[31:0] ([syncword2_set3/2/1/0: b1 0x2b/2c/2d/2e]). [rx] i) continuous output mode (to host) set rxdio_ctrl[1:0] ([dio_set: b0 0x0c(7-6)]) =0b01. after rx_on (set_trx[3:0] ([rf_status: b0 0x0b(3-0)])=0x6) , dclk is output continuously. rx data (demodulated data) is output from dio pin at falling edge of dclk. rx data is not stored into rx_firo. note: for details of timing, please refer to the ?rx? in the ?timing chart?. dio(gpio0-3,ext_clk) tx_on command tx data dclk(gpio0-3,ext_clk) preamble syncword data-field trx_off command tx_on dio(gpio0-3,ext_clk) rx_on command rx data dclk(gpio0-3,ext_clk) preamble syncword data-field trx_off command rx_on fedl7344c/e/j-05 ml7344c/e/j 52/154 ii) data output mode 1 (to host) set rxdio_ctrl[1:0] ([dio_set: b0 0x0c(7-6)]) =0b10. after syncword detection, rx data is buffered in rx_f ifo. rx data buffering will continue until rx sync signal (sync) becomes ?l?. by setting dio_start ([dio_set: b0 0x0c(0)])=0b1, top data of buffered data will be output through dio interface (dio/dclk). (rx data is output at falling edge of dclk). however, if dio_start setting is done after 64 byte timing, the top byte will be over written. if all buffered data is output until sync becomes ?l?, rx completion interrupt (int[8] group 2) will be generated. after rx completion, ready to receive next packet. note: 1. rx data buffering in rx_fifo is accessed byte by byte. dio_start should be issued after 1 byte access cycle upon syncword detection. 2. this mode does not process l-field. field checking function is not supported. dio(gpio0-3,ext_clk) rx_on rx_on command rx data dclk(gpio0-3,ext_clk) trx_off command buffering to rx_fifo rx sync signal preamble syncword data-field dio_start =0b1 fedl7344c/e/j-05 ml7344c/e/j 53/154 if dio_start is issued before syncword detection, data is not buffered in rx_fifo and rx data after syncword detection will be output at falling edge of dclk . in order to complete rx before sync becomes ?l?, dio rx completion setting (dio_rx_complete([dio_set: b0 0x0c(2)]=0b1) is necessary. after dio_rx_complete setting, ready to receive the next packet. iii) data output mode 2 (to host) set rxdio_ctrl[1:0] ([dio_set: b0 0x0c(7-6)])=0b11. only data-field of rx data is buffered in rx_fifo. rx data indicated by l-field is stored in rx_fifo. by dio_start([dio_set: b0 0x0c(0)])=0b1, top data of buffered data will be output through dio interface (dio/dclk). (rx data is output at falling edge of dclk). however, if dio_start setting is done after 64 byte timing, the top byte will be overwritten. if all data indicated by l-field is output, rx completion interrupt (int[8] group2) will be generated. after rx completion, ready to receive next packet. length information is stored in [rx_pkt_len_h/l: b0 0x7d/7e] registers. this mode support fileld check function. note: rx data buffering in rx_fifo is byte by byte access. dio_start should be issued after elapsed time from syncword detection to l-field length + over 1byte access time. dio_start=0b1 dio(gpio0-3,ext_clk) rx_on rx_on command rx data dclk(gpio0-3,ext_clk) trx_off command buffering to rx_fifo rx sync signal preamble syncword data-field dio_rx_complete =0b1 dio(gpio0-3,ext_clk) rxon rx data dclk(gpio0-3,ext_clk) preamble syncword data-field l-field dio_start=0b1 rx_on command trx_off command fedl7344c/e/j-05 ml7344c/e/j 54/154 (2)in case of using sdi/sdo pins (sharing with spi interface) if sdi and sdo pins are used as dclk/dio, dclk/dio should be controlled as follow. (below dio/dclk vertical line part indicate output or input period) both sdo_cfg and sdi_cfg ([sdi/ext_pa_ctrl:b0 0x53(5,4)]) should be set 0b1 [tx] i) continuous input mode (from host) set txdio_ctrl[1:0] ([dio_set: b0 0x0c(5-4)]) =0b01. after tx_on (set_trx[3:0] ([rf_status: b0 0x0b(3-0)])=0x9) , during scen pin is ?h?, dclk is output from sdo pin., tx data can be input from dio pin at falling edge of dclk. tx data must be encoded data. after trx_off is issued (set_trx[3:0] ([rf_status: b0 0x0b(3-0)])=0x8), dclk output will stop. during dclk output, if scen pin becomes ?l?, dclk output will stop. (spi access has priority) note: not to access spi until tx completion. during packet transmission, if spi access is attempted by the host, tx data error can be expected. ii) data input mode (from host) set txdio_ctrl[1:0] ([dio_set: b0 0x0c(5-4)])=0b10. after tx_on, when scen is ?h?, dclk is output from sdo pin during data input period after syncword. at falling edge of dclk, tx data should be input to sdi from the host. after trx_off is issued (set_trx[3:0] ([rf_status: b0 0x0b(3-0)])=0x8), dclk output will stop. during dclk output period, if scen becomes ?l?, dclk output will stop. (spi access has a priority) tx_on command trx_off command dio(sdi) txon tx data dclk(sdo) preamble syncword data-field scen tx_on command trx_off command dio(sdi) txon tx data dclk(sdo) preamble syncword data-field scen fedl7344c/e/j-05 ml7344c/e/j 55/154 note: not to access spi until tx completion. during packet transmission, if spi access is attempted by the host, tx data error can be expected. [rx] i) continuous output mode (to host) set rxdio_ctrl[1:0] ([dio_set: b0 0x0c(7-6)])=0b01. after rx_on (set_trx[3:0]([rf_status: b0 0x0b(3-0)])=0x6) issued, during scen is ?h? period, dclk is output from sdo pin, rx data is output from sdi pin at falling edge of dclk. after trx_off issuing(set_trx[3:0] ([rf_status: b0 0x0b(3-0)])=0x8), dclk/dio output will stop. even if dclk/dio are output, when scen becomes ?l?, dclk /dio will stop. (spi access has a higher priority) note: not to access spi until rx completion. during packet tran smission, if spi access is attempted by the host, rx data error can be expected. rxon rx data scen dio(sdi) dclk(sdo) rx_on command trx_off command preamble syncword data-field fedl7344c/e/j-05 ml7344c/e/j 56/154 ii) data ouput mode 1 or data output mode 2 (to host) set rxdio_ctrl[1:0] ([dio_set: b0 0x0c(7-6)])=0b10/11 after rx_on, rx data upon syncword (output mode 1) or rx data upon l-fileld (output mode 2) is buffered in rx_fifo. during scen is ?h?, by dio_start([d io_set: b0 0x0c(0)])=0b1, top data of buffered data will be output through dio interface (dio/dclk). (rx data is output at falling edge of dclk). other output condition is same as the case of using gpio:/ect_clk pins. after trx_off isuing, dclk/dio output will stop. even during dclk/dio are output period, if scen becomes ?l?, dclk/dio output will stop. (spi access has a priority) (in case of data output mode1) note: not to access spi until rx completion. during packet tran smission, if spi access is attempted by the host, rx data error can be expected. rxon rx data scen dio_rx_complete =0b1 dio(sdi) dclk(sdo) preamble syncword data-field dio_start =0b1 rx_on command trx_off command fedl7344c/e/j-05 ml7344c/e/j 57/154 (3)dclk output method in data output mode 2, decoded data is output. therefore, the dclk output section in a output interval changes with the coding method. dclk output section is as follows. in othe modes, undecoded data is input or output. dclk is output continuously. then, it is not depend on the coding method. i) data output mode 2 ii) tx continuous input mode or rx continuous mode iii) tx data input mode / rx data output mode1 output interval nrz: : 8 cycle manchester :16 cycle 3 out of 6 :12 cycle dclk clock output (8 cycle) output interval 1 cycle=1/data rate[bps] (*) the nuber of cycle per 1 byte nrz : 8 cycle manchester :16 cycle 3 out of 6 :12 cycle dclk dclk tx: the timing during transmitting the last 2 bit syncword rx: dio_start issue 1 cycle=1/data rate[bps] 1 cycle=1/data rate[bps] (*) the nuber of cycle per 1 byte nrz : 8 cycle manchester :16 cycle 3 out of 6 :12 cycle fedl7344c/e/j-05 ml7344c/e/j 58/154 timer function w ake-up timer ml7344 has automatic wake-up function using wake-up timer. the following operations are possible by using wake-up timer. ? upon timer completion, automatically wake-up from sl eep state. after wake-up operation can be selected as rx_on state or tx_on state by wakeup_mode ([sleep/wu_set: b0 0x2d(6)]). ? by setting wut_1shot_mode ([sleep/wu_set: b0 0x2d(7)]), continuous wake-up operation (interval operation) or one shot operation can be selected ? in interval operation, if rx_on/tx_on state is caused by wake-up timer, continuous operation timer is in operation. ? after moving to rx_on state by wake-up timer, when continuous operation timer completed, move to sleep state automatically. however, if syncword is detected before timer completion, rx_on state will be maintained. in this case, ml7344 does not go back to sleep state automatically. sleep setting (sleep_en ([sleep/wu_set: b0 0x2d(0)])=0b1) is necessary to go back to sleep state. however, if rxdone_ mode[1:0] ([rf_status_ctrl:b0 0x0a(3-2)])=0b11, after rx completion, move to sleep state automatically. for ml7344c, when continuous operation timer co mpleted, the condition for continuing reception is selected from sync word detection or field check result by rcv_cont_sel([c_check_ctrl: b0 0x1b(5)]). ? after moving to tx_on state by wake-up timer, when continuous operation timer completed, move to sleep state automatically. ? after wake-up by combining with high speed carrier checking mode, cca is automatically performed, if idle is detected, able to move to sleep state immedi ately. for details, please refer to the ?(3) high speede carrier detection mode?. ? by setting wu_clk_source ([sleep/wu_set:b0 0x2d(2)]), clock source for wake-up timer are selectable from ext_clk pin or on-chip rc osc. wake-up interval, wake-up timer interval and continuous operation timer can be calculated in the following formula. wake-up interval [s] = wake-up timer interval [s] + continuous operation timer [s] wake-uptimer interval [s] = wake-up timer clock cycle * division setting ([wut_clk_set: b0 0x2e(3-0)]) * (wake-up timer interval setting ([wut_interval_h/l: b0 0x2f/0x30]) + 1) continuous operation timer [s] = wake-up timer clock cycle * division setting([wut_clk_set: b0 0x2e(7-4)]) * (continuous operation timer setting ([wu_duration: b0 0x31]) ? 1) note: ? in case of moving to tx_on state after wake-up, move to sleep state when timer completed even in the middle of transmission. continuous oeration timer should be set in such manner that timer completing after tx completion. ? wudt_clk_set[3:0] ([wut_clk_set: b0 0x2e(7-4)]) and wut_clk_set[3:0] ([wut_clk_ set: b0 0x2e (3-0)]) can be set independently. in case of using continuous operation timer, please set the same value as wudt_clk_set as wut_clk_set. ? minimum value for wake-up timer interval setting ([wut_interval_h/l: b0 0x2f/0x30]) is 0x02. and minimum value for continuous operation timer setting ([wu_duration: b0 0x31]) is 0x01. ? be noted that the syncword detection is not issued when in dio mode with rxdio_ctrl([dio_set: b0 0x0c(7-6)])=0b01. therefore , when continuous operation timer completed, forcibly move to sleep state. fedl7344c/e/j-05 ml7344c/e/j 59/154 (1) interval operation [rx] after wake-up, rx_on state. if continuous operation timer completed before syncword detection, automatically move to sleep state. if syncword detect ed, continue rx_on. after rx completion, conitune operation defined by rxdone_mode[1:0] ([rf_status_ctrl:b0 0x0a(3-2)]). [tx] after wake-up, tx_on state. after tx completion, continue operation defined by txdone_mode[1:0] ([rf_status_ctrl: b0 0x08(1-0)]) . if continuous operation timer completed, automatically return to sleep state. so continuous operation timer has to be set so that timer completion occur after tx completion. rxon txon wake-up timer continuous operation timer lsi state rxon txon wake-up timer continuous operation timer lsi state tx completion and move to idle state. in case of txdone_mode[1:0]=0b00 wake-up operation enables setting wake-up timer operation period [wut_interval_h/l: b0 0x2f/0x30) continuous operation timer range [wu_duration: b0 0x28] continuous operation timer completion, move to sleep state. sleep txon tx data write to tx_fifo sleep idle txon sleep idle txon wake-up timer enable setting wake-up timer operation range [wut_interval_h/l: b0 0x2f/0x30] sleep rxon continuous operation timer range [wu_duration: b0 0x31] before continuous operation timer completion, syncword detected. a fter rx completion, move to sleep state by sleep command. *1 if not issuing sleep command, continue operation defined by rxdone_mde[1:0] sleep rxon sleep rxon sleep *1 rxon sleep a fter wake-up timer completion , move to rx_on state. continuous operation timer completion move to sleep state. [sleepwu_set: b0 0x2d(6-4)]=0b011 [sleep/wu_set: b0 0x2d(6-4)]=0b111 fedl7344c/e/j-05 ml7344c/e/j 60/154 (2) 1 shot operation [rx] after wake-up timer completion, move to rx_on state. and continue rx_on state. move to sleep state by sleep command. if wake-up timer interval setting ([wut_interval_h/l:b0 0x2f/0x30]) is maintained, after re-issuing sleep command, 1 shot operation will be activated again. if rx completed during rx_on, continue operation defined by rxdone_ mode[1:0] ([rf_status_ ctrl: b0 0x0a(3-2)]) . same manner in tx_on state. rxon txon wake-up timer wake-up operation enable setting continuous operation timer wake-up timer operation range [wut_interval_h/l: b0 0x2f/0x30] lsi state a fter sleep command, move to sleep state. sleep rxon sleep rxon wake-up timer completion and move to rxon state rx_on is maintained if sleep command is not issued. [sleepwu_set: b0 0x2d(7-4)]=0b1011 fedl7344c/e/j-05 ml7344c/e/j 61/154 (3) combination with high speed carrier detection [intetval operation] after wake-up timer completion, move to rx_on state. then perform cca. if no carrier detected, automatically move to sleep state. if carrier det ected, maintaining rx_on state and perform suncword detection. if continuous operation timer completed before syncword detection, automatically move to sleep state. and if syncword detected, continue rx_on state. [1 shot operation] after wake-up timer completion, move to rx_on state. and perform cca to check carrier. if no carrier detected, go back to sleep state automatically. after wake-up timer completion, wake-up to check the carrier again. if carrier is detected, continue rx state. able to go back to sleep by setting sleep parameters. rxon txon wake-up timer wake up operation enable setting continuous operation timer wake-up timer operation range [wut_interval_h/l: b0 0x2f/0x30] lsi state sleep rxon continuous operation timer range [wu_duration: b0 0x28] syncword detection before continuous operation timer completion a fter rx completion, move to sleep state by command. sleep rxon sleep rxon sleep rxon sleep no carrier detection, and move to sleep state. carrier detected, and continue rx_on. continuous operation timer completion, and move to sleep state. [sleep/wu_se t : b0 0x2d(7-4)]=0b0011 fast_det_mode_en([cca_ctrl: b0 0x39(3)])=0b1 rxon txon continuous operation timer wake-up timer operation range [wut_interval_h/l: b0 0x2f/0x30] lsi state wake-up operation enable setting sleep rxon by sleep command go to sleep state. sleep rxon sleep sleep no carrier detected. go to sleep state carrier detected, continue rxon sleep rxon [sleepwu_set: b0 0x2d(7-4)]=0b1011 fast_det_mode_en([cca_ctrl: b0 0x39(3)])=0b1 fedl7344c/e/j-05 ml7344c/e/j 62/154 general purpose timer ml7344 has general purpose timer. 2 channel of timer are able to function independently. clock sources, timer setting can be programmed independently. when timer is completed, general purpose timer 1 interrupt (int[22] group3) or general purpose timer 2 interrupt (int[23] group3)will be generated. general timer interval can be programmed as the following formula. general purpose timer interval[s] = general purpose timer clock cycle * division setting ([gt_clk_set: b0 0x33]) * general purpose timer interval setting ([gt1_timer: b0 0x34] or [gt2_timer: b0 0x35]) by setting gt2/1_clk_source ([gt_set: b0 0x32(5,1)]), clock sources for general purpose timer can be selectable from wake-up timer clock or 2mhz. fedl7344c/e/j-05 ml7344c/e/j 63/154 frequency setting function c hannel frequency setting maximum 256 channels can be selected (ch#0 -ch#255) by the following resisters. frequency register tx [txfreq_i: b1 0x1b], [txfreq_fh: b1 0x1c], [txfreq_fm: b1 0x1d] and [txfreq_fl: b1 0x1e] ch#0 frequency rx [rxfreq_i: b1 0x1f], [rxfreq_fh: b1 0x20], [rxfreq_fm: b1 0x21] and [rxfreq_fl: b1 0x22] channel space - [ch_space_h: b1 0x23] and [ch_space_l: b1 0x24] channel setting - [ch_set: b0 0x09] (1) channel frequency setting overview [channel frequency setting] using above registers, channel frequency is defined as following formula. channel frequency = i) ch#0 frequency + ii) channel sp ace * iii) channel setting [channel frequency allocation image] frequency ii) channel space setting i) ch#0 frequency setting iii) channel setting (setting nth channel) channel no. ? 0 1 2 3 n 255 fedl7344c/e/j-05 ml7344c/e/j 64/154 note: the channel frequency to be selected must meet the following conditions. if the following conditions cannot be met, please change channel #0 frequency or use other channels. if this formula cannot be met, expected frequency is not functional or pll may not be locked. (f mck1 *n + 1mhz ) / n_div channel frequency (f mck1 *(n+1) ? 1mhz ) / n_div f mck1 : master clock frequency n_div = 1 (pll_mode ([pll_div_set: b1 0x1a (4)])=0b0) 2 (pll_mode ([pll_div_set: b1 0x1a (4)])=0b1) n = integer [calculation example above ?a? range] condition: master clock 26mhz, n_div=1(pll_mode=0b0), n=16 (26*16+1)mhz channel frequency to be used (26*(16+1)-1) 417 mhz channel frequency to be used 441mhz note: ?ch#0 frequency (hz)? and ?channle space (hz)? may have error (hz). then the ?channel frequency error (hz)? is defined as following formula. channel frequency error (hz) = ch#0 frequency error (hz) + channel space error (hz)* channel setting when changing ?channel frequency? by setting ?channel setting? without ?ch#0 frequency? change, the ?channel frequency error? will become larger than by setting both ?ch#0 frequency? and ?channel setting?. if the ?channle frequency error? is larger than exp ection, please consider to change ?ch#0 frequency?. unusable frequency usable frequency (f mck1 *n )/n_div frequency (f mck1 *(n+1))/n_div a fedl7344c/e/j-05 ml7344c/e/j 65/154 (2) channel #0 frequency setting tx frequency can be set by [txfreq_i: b1 0x1b], [txfreq_fh: b1 0x1c], [txfreq_fm: b1 0x1d] and [txfreq_fl: b1 0x1e]. rx frequency can be set by [rxfreq_i: b1 0x1f], [rxfreq_fh: b1 0x20], [rxfreq_fm: b1 0x21] and [rxfreq_fl: b1 0x22]. when enabling pll 1/2 division mode by setting pll_mode([pll_div_set:b1 0x1a(4)])= 0b1, calcurated with fref =f mck1 /2 in the following formula. channel #0 frequency setting can be caluculated using the following formula. ref rf f f i = (integer part) 20 2 ? ? ? ? ? ? ? ? ? ? ? ?= i f f f ref rf (integer part) here rf f :channel #0 frequency ref f :pll reference frequency (=master clock frequency: f mck1 ) i :integer part of frequency setting f :fractional part of frequency setting i (hex) is set to [txfreq_i: b1 0x1b], [rxfreq_i: b1 0x1f] registers. f (hex.) is set to the following registers. for tx, from msb, set in order of [txfreq_fh: b1 0x1c], [txfreq_fm: b1 0x1d], [txfreq_fl: b1 0x1e] registers. for rx, from msb, set in order of [rxfreq_fh: b1 0x20], [rxfreq_fm: b1 0x21], [rxfreq_fl: b1 0x22] registers. frequency error ( err f ) is calculated as follows : rfref err ff f if ?? ? ? ? ? ? ? += 20 2 [example] when set tx channel #0 frequency to 426mhz (master clock 26mhz), the calculations are as follows. m h z mhz i 26 426 = (integer part) =16(0x10) 20 2 26 426 ? ? ? ? ? ? ? ? = i mhz mhz f (integer part)=403298(0x062762) [txfreq_i: b1 0x1b] = 0x10 [txfreq _fh: b1 0x1c] = 0x06 [txfreq _fm: b1 0x1d] = 0x27 [txfreq _fl: b1 0x1e] = 0x62 frequency error err f is as follows: hz mhz mhz f err 45.11 426 26 2 403298 16 20 ?= ?? ? ? ? ? ? ? += fedl7344c/e/j-05 ml7344c/e/j 66/154 (3) channel space setting channel space can be set by [ch_space_h: b1 0x23], [ch_space_l: b1 0x24] registers. hexadecimal values calculated in the following formula should be set to [ch_space_h: b1 0x23], [ch_space_l: b1 0x24] registers. (msb->lsb order) when enabling pll 1/2 division mode by setting pll_mode ([pll_div_set:b1 0x1a(4)])=0b1, calcurated with fref =f mck1 /2 in the following formula. channel space is from the center frequency of give n channel to adjacent channel center frequency. channel space setting value can be calculated using the following formula: 20 2 _ ? ? ? ? ? ? ? ? ? ? ? = ref sp f f space ch (integer part) here :_ space ch channel space setting : sp f channel space [mhz] : ref f pll reference frequency (=master clock frequency : f mck1 ) [example] when set channle space to 25khz (master clock 26mhz), the calculation is as follows. 20 2 26 025.0 _ ? ? ? ? ? ? ? = mhz mhz space ch (integer part) = 1008 (0x03f0) [ch_space_h: b1 0x23] = 0x03 [ch_space_l: b1 0x24] = 0xf0 fedl7344c/e/j-05 ml7344c/e/j 67/154 if frequency setting if frequency is 200khz. if frequency corresponds to each oepration frquency must be selected as below. operating frequency 169mhz (ml7344e) 315 to 450mhz (ml7344j) 470 t0 510mhz (ml7344c) pll division setting [pll_div_set:b1 0x1a] 0x10 0x00 if frequency setting [if_freq_h/l:b0 0x54-55] 0x1f81 0x0fc0 if frequency setting value can be calculated using the following formula: 20 2 )2/( _ ? ? ? ? ? ? ? ? ? ? ? = ref if f f freqif (integer part) here freqif _ : if frequency setting : if f if frequency [mhz] : ref f pll reference frequency (=master clock frequency: f mck1 ) [example] ml7344c/j if_freq= {(0. 2mhz / 2) / 26mhz} * 2 20 (integer part) = 4032 (0x0fc0) [if_freq_h: b0 0x54] = 0x0f [if_freq_l: b0 0x55] = 0xc0 [example] ml7344e if_freq= {(0. 2mhz / 2) / (26/2)mhz} * 2 20 (integer part) = 8065 (0x1f81) [if_freq_h: b0 0x54] = 0x1f [if_freq_l: b0 0x55] = 0x81 fedl7344c/e/j-05 ml7344c/e/j 68/154 modulation setting ml7344 supports gfsk modulation and fsk modulation. (1) gfsk modulation setting by setting gfsk_en([data_set1: b0 0x07(4)])=0b1, gfsk mode can be selected. in gfsk modulation, frequency deviation can be set by [gfsk_dev_h: b1 0x30] and [gfsk_dev_l: b1 0x31] registers and gaussian filter can be set by [fsk_dev0_h/gfil0: b1 0x32] to [fsk_dev3_h/gfil6: b1 0x38] registers. when enabling pll 1/2 division mode by setting pll_mode ([pll_div_set:b1 0x1a(4)])=0b1, calcurated with fref =f mck1 /2 in the following formula. i) gfsk frequency deviation setting f_dev value can be calculated as the following formula: 20 2 _ ? ? ? ? ? ? ? ? ? ? ? = ref dev f f devf (integer part) here devf _ : frequency deviation setting : dev f frequency deviation [mhz] : ref f pll reference frequency (= master clock frequency: f mck1 ) [example] when set frequency deviation to 50kh (master clock 26mhz), the calculation is as follows. f_dev = {0.05mhz 26mhz} 2 20 (integer value) = 2016 (0x07e0) [gfsk_dev_h: b1 0x30] = 0x07 [gfsk_dev_l: b1 0x31] = 0xe0 ii) gaussian filter setting bt value of gaussian filter and setting value to related registers are shown in the below table. bt value register 0.5 1.0 [fsk_dev0_h/gfil0: b1 0x32] 0x49 0x00 [fsk_dev0_l/gfil1: b1 0x33] 0xa7 0x10 [fsk_dev1_h/gfil2: b1 0x34] 0x0f 0x04 [fsk_dev1_l/gfil3: b1 0x35] 0x14 0x0d [fsk_dev2_h/gfil4: b1 0x36] 0x19 0x1e [fsk_dev2_l/gfil5: b1 0x37] 0x1d 0x32 [fsk_dev3_h/gfil6: b1 0x38] 0x1e 0x3c note: gfsk filter coefficient setting register and fsk frequency deviation setting register are common. in gfsk mode, filter coefficient applies to this register. in fsk mode, frequency deviation applies to this register. fedl7344c/e/j-05 ml7344c/e/j 69/154 (2) fsk modulation setting by setting gfsk_en([data_set1: b0 0x07(4)])=0b0, fsk mode can be selected. fine frequency deviation can be set by [fsk_dev0_h/gfil0: b1 0x32] to [fsk_dev4_l: b1 0x3b] registers. by adjusting [fsk_tim_adj4-0: b1 0x3c-40] registers, fsk timing can be fine tuned. frequency deviation setting timing setting symbol register name address function symbol register name address function i fsk_fdev0_h/gfil0 fsk_fdev0_l/gfil1 b1 0x32/33 i fsk_tim_adj4 b1 0x3c ii fsk_fdev1_h/gfil2 fsk_fdev1_l/gfil3 b1 0x34/35 ii fsk_tim_adj3 b1 0x3d iii fsk_fdev2_h/gfil4 fsk_fdev2_l/gfil5 b1 0x36/37 iii fsk_tim_adj2 b1 0x3e iv fsk_fdev3_h/gfil6 fsk_fdev3_l b1 0x38/39 iv fsk_tim_adj1 b1 0x3f v fsk_fdev4_h fsk_fdev4_l b1 0x3a/3b frequency deviation resolution: approx.25 hz v fsk_tim_adj0 b1 0x40 modulation timing 4.3mhz/13 mhz counter value (*1) (*1) modulation timing resolution can be changed by fsk_clk_set ([fsk_ctrl: b1 0x2f(0)]). note: gfsk filter coefficient setting register and fsk frequency deviation setting register are common. in gfsk mode, filter coefficient applies to this register. in fsk mode, frequency deviation applies to this register. tx_fsk_pol ([data_set1:b0 0x07(6)]) = 0b0 setting + f - f 1 output i ii iii v i iv 0 output i iii ii iv v i iii ii iv i ii iii iv i ii ii iii iii iv iv v v fedl7344c/e/j-05 ml7344c/e/j 70/154 rx related function afc fun ction ml7344 supports afc function. master clock frequency accuracy (max. 10ppm) between transmitter and receiver can be compensated by this function. using th is function, stable rx sensitivity and interference blocking performance can be achieved. this function can be enabled by setting afc_en([afc/gc_ctrl: b1 0x15(7)])=0b1. afc range is defined by afc_lim_off ([demod_set0:b1 0x56(2)]. when setting 0b0 (limit on), afc range is 9ppm. when setting 0b1 (limit off), 10ppm afc range is avilable. energy detection value (ed value) acquisition function ml7344 supports calculating energy detection value (ed va lue) based on received signal strength indicator (rssi). ed value acquisition can be enabled by setting ed_calc_en ([ed_ctrl: b0 0x41(7)])=0b1 and as soon as transition to rx_on state, automatically start acquiring ed value. during rx_on state, ed value constantly updated. ed value is not rssi value at given timing, but average values. number of average times can be specified by ed_avg[2:0] ([ed_ctrl: b0 0x41(2-0)]). after acquiring specified average ed value, ed_done ([ed_ctrl: b0 0x41(4)]) becomes ?0b1? and ed_value[7:0] ([ed_rslt: b0 0x3a]) is updated. ed_done bit will be cleared if one of the following conditions are met. 1. gain is switched.. 2. once stopping ed value acquisition and then resume it timing from ed value starting point to ed value acquisition is calculated as below formula. ed value average time = ad conversion time (18.5 s/14.7 s) * (number of average times + 8(deley)). note: ad conversion time can be slected by adc_clk_sel([adc_clk_set: b1 0x08(4)]). reset value is 1.73mhz and ad conversion time is 18.5 s. digital filter delay is ?ad conversion time * 8?. the timing example is as follows: set adc_clk_sel ([adc_clk_set: b1 0x08(4)]) =0b1. (1.73 mhz) set ed_avg[2:0] ([ed_ctrl: b0 0x41(2-0)])=0b011. (8 times averaging) rssi value (internal signal) ad conversion (18.5 s) ed_done ([ed_ctrl:b0 0x41(4)]) ed value calculation execution flag (internal signal) ed_value[7:0] [ed_rslt: b0 0x3a] ed value averaging period (18.5 s*(8+8)=296 s) rssi 1 ed 1-8 invalid compensation and averaging ed 2-9 constantly update by moving average ed 3-10 rssi 2 rssi 3 rssi 4 rssi 5 rssi 6 rssi 7 rssi 8 rssi 9 rssi 10 rssi 8 fedl7344c/e/j-05 ml7344c/e/j 71/154 cca (clear channel assessment) function ml7344 supports cca function. cca function is to make a judment wheher the specified frequency channel is in-use or available. normal mode, continuous mode and idle detection mode are supported as following table. [cca mode setting] [cca_ctrl: b0 0x39] bit4 (cca_en) bit5 (cca_cpu_en) bit6 (cca_idle_en) normal mode 0b1 0b0 0b0 continuous mode 0b1 0b1 0b0 idle detection mode 0b1 0b0 0b1 (1) normal mode normal mode determines idle or busy. cca (normal mode) will be executed when rx_on is issued whille cca_en(cca_ctrl: b0 0x39(4)])=0b1, cca_cpu_en (cca_ctrl: b0 0x39(5)])=0b0 and cca_idle_en(cca_ctrl: b0 0x39(6)])=0b0 are set. cca judgement is determined by average ed value in [ed_rslt: b0 0x3a] register and cca threshold value defined by [cca_lvl: b0 0x37] register. if average ed value exceeds the cca threshold value, it is considered as ?busy?. and cca_rslt[1:0]([cca_ctrl: b0 0x39(1-0)]) =0b01 is set if average ed value is smaller than cca threshold value and maintains idle detection period which is defined by idle_wait[9:0] of the [idle_wait_l: b0 0x3b], [idle_wait_h: b0 0x3c] registers, it is considered as ?idle?. and cca_rslt[1:0] =0b00 is set. for details operation of cca_idle_wait[9:0], please refer to ?idle detection for long time period? if ?busy? or ?idle? state is detected, cca completion interrupt (int[18] group3) is generated, cca_en bit is cleared to 0b0 automatically. upon clearing cca completion interrupt, cca_rslt[1:0] are reset to 0b00. therefore cca_rslt[1:0] should be read before clearing cca completion interrupt. if an ed value exceeds the value defined by [cca_ignore_lvl: b0 0x36] register, and a given ed value is included in the averaging target of ed value calculation, idle judgement is not performed. in this case if average ed value exceed cca threshold value, it is cons idered as ?busy? and cca operation is terminated. if average ed value is smaller than cca threshold value, idle judgement is not determined. and cca_rslt[1:0] indicates 0b11. cca operation continues until ?busy? is determined or the gievn ed value is out of averaging target and ?idle? is determined. for details operation of ed value execeeding [cca_ignore_lvl: b0 0x36] register, please refer to ?idle determination exclusion under strong signal input?. time from cca command issue to cca completion is in the formula below. [idle detection] cca execution time = (ed value average times + dgital filter delay + idle_wait setting) * ad conversion time [busy detection] cca execution time = (ed value average times + digtal filter delay)* ad conversion time note: 1. above formula does not consider idle judgement exclusion based on [cca_ignore_lvl: b0 0x36] register. for details, please refer to ?idle detection exclusion under strong signal input?. 2. ad conversion time can be slected by adc_clk_sel([adc_clk_set: b1 0x08(4)]). adc_clk_sel=0b0:14.7 s , 0b1:18.5 s (default) 3. digital filter delay is ?ad conversion time * 8?. fedl7344c/e/j-05 ml7344c/e/j 72/154 the following is timing chart for normal mode. set adc_clk_sel ([adc_clk_set: b1 0x08(4)]) =0b1. (1.73 mhz) set ed_avg[2:0] ([ed_ctrl: b0 0x41(2-0)])=0b011. (8 times average) set idle_wait[9:0] ([idle_wait_l/h:b0 0x 3c/3b(1-0)])=0b00 0000 0000 (idle detection 0s) [idle detection case] [busy detection case] ed value (internal signal) cca_rslt[1:0] [cca_ctrl: b0 0x39(1-0)] int[18] (cca completion) [int_source_grp3: b0 0x0f(2)] cca_en [cca_ctrl: b0 0x39(4)] ed_value[7:0] [ed_rslt: b0 0x3a] ad conversion (18.5 s) ed value average period (16 s*8=128 s) 0b10 (cca on-going) ed1 ed ( 0-7 ) 0b00 (idle) *1 averaging cca execution period (min.296 s) < cca_lvl b0 0x37 idle_wait[9:0] should be set, for idle detection for longer period. ed0 ed3 ed2 ed5 ed4 ed7 ed6 ed value (internal signal) cca_rslt[1:0] [cca_ctrl: b0 0x39(1-0)] int[18] (cca completion) [int_source_grp3: b0 0x0f(2)] cca_en [cca_ctrl: b0 0x39(4)] ed_value[7:0] [ed_rslt: b0 0x3a] ad conversion (18.5 s) ed value average period (16 s*8=128 s) 0b10 (cca on-going) ed1 ed ( 0-7 ) 0b01 (busy) *1 averaging cca execution period (min.296 s) > cca_lvl b0 0x37 idle_wait[9:0] should be set, for idle detection for longer period. ed0 ed3 ed2 ed5 ed4 ed7 ed6 fedl7344c/e/j-05 ml7344c/e/j 73/154 note: *1 digital filter delay is ?ad conversion time * 8?. ad conversion time can be slected by adc_clk_sel ([adc_clk_set: b1 0x08(4)]). reset value is 1.73mhz and ad conversion time is 18.5 s. (2) continuous mode continuous mode continues cca untill terminated by the host mcu. cca continuous mode will be executed when rx_on is issued while cca_en(cca_ctrl: b0 0x39(4)])=0b1, cca_cpu_en(cca_ctrl: b0 0x39(5)])=0b1 and cca_idle_en(cca_ctrl: b0 0x39(6)])=0b0 are set. like normal mode, cca judgement is determined by average ed value in [ed_rslt: b0 0x3a] register and cca threshold defined by [cca_lvl: b0 0x37] register. if average ed value exceeds the cca threshold value, it is considered as ?busy?. and cca_rslt[1:0]([cca_ctrl: b0 0x39(1-0)]) = 0b01 is set. if average ed value is smaller than cca threshold value and maintains idle detection period which is defined by idle_wait[9:0] of the [idle_wait_l: b0 0x3b], [idle_wait_h: b0 0x3c] registers, it is considered as ?idle?. and cca_rslt[1:0] =0b00 is set. for details operation of cca_idle_wait[9:0], please refer to ?idle detection for long time period?. if an ed value exceeds the value defined by [cca_ignore_lvl: b0 0x36] register, a given ed value is included in the averaging target of ed value calculation, idle judgement is not performed. in this case if average ed value exceeds cca threshold level, it is considered as ?busy? and cca_rslt[1:0] indicates 0b01. if average ed value is smaller than cca threshold level, idle judgement is not determined. and cca_rslt[1:0] indicates 0b11. for details operation of ed value execeeding [cca_ignore_lvl: b0 0x36] register, please refer to ?idle determination exclusion under strong signal input?. continuous mode does not stop when ?busy? or ?idle? is detected. cca operation continues until 0b1 is set to cca_stop([cca_ctrl: b0 0x39(7)]). result is updated every time ed value is acquired. cca completion interrup (int[18] group3) will not be generated. fedl7344c/e/j-05 ml7344c/e/j 74/154 the following is timing chart for continuous mode. set adc_clk_sel ([adc_clk_set: b1 0x08(4)]) =0b1. (1.73 mhz) set ed_avg[2:0] ([ed_ctrl: b0 0x41(2-0)])=0b011. (8 times average) set idle_wait[9:0] ([idle_wait_l/h:b0 0x 3c/3b(1-0)])=0b00 0000 0000 (idle detection 0s) [busy to idle transition, terminated with cca_stop] note: *1 digital filter delay is ?ad conversion time * 8?. ad conversion time can be slected by adc_clk_sel ([adc_clk_set: b1 0x08(4)]). reset value is 1.73mhz and ad conversion time is 18.5 s. ed (21-28) ed (43-50) ed value (internal signal) ad conversion (18.5 s) ed value average period ( 148 s ) 0b10 (cca on-going) ed0 ed7 ed8 ed28 0b00 (idle) ed_value[7:0] [ed_rslt: b0 0x3a] invalid averaging > cca_lvl b0 0x37 ed (0-7) fedl7344c/e/j-05 ml7344c/e/j 76/154 the following is timing chart for idle detection mode. set adc_clk_sel ([adc_clk_set: b1 0x08(4)]) =0b1. (1.73 mhz) set ed_avg[2:0] ([ed_ctrl: b0 0x41(2-0)])=0b011. (8 times average) set idle_wait[9:0] ([idle_wait_l/h:b0 0x 3c/3b(1-0)])=0b00 0000 0000 (idle detection 0s) [upon busy detection, continue cca and idle detection case] note: *1 digital filter delay is ?ad conversion time * 8?. ad conversion time can be slected by adc_clk_sel ([adc_clk_set: b1 0x08(4)]). reset value is 1.73mhz and ad conversion time is 18.5 s. ed (20-27) ed (22-29) ed value (internal signal) ad conversion (18.5 s) ed value average period ( 148 s ) 0b10 (cca on-going) ed0 ed7 ed8 ed27 0b00 (idle) ed_value[7:0] [ed_rslt: b0 0x3a] invalid averaging > cca_lvl b0 0x37 ed (0-7) fedl7344c/e/j-05 ml7344c/e/j 78/154 the following is timing chart for idle detemination exclusion under strong signal. set adc_clk_sel ([adc_clk_set: b1 0x08(4)]) =0b1. (1.73 mhz) set ed_avg[2:0] ([ed_ctrl: b0 0x41(2-0)])=0b011. (8 times average) set idle_wait[9:0] ([idle_wait_l/h:b0 0x3c/3b(1-0)])=0b00 0000 0111 (idle detection 129.5s) [during idle_wait counting, detected extremly strong signal. after the given signal is out of averaging target, idle detection case] ed7 invalid ed8 ed13 ed14 0x001 0x006 0b11 (on-going) 0x000 ed value>cca_ignore_lvl detection and reset due to extreme strong signal detection, cca_rslt is not indicating idle. cca_rslt[1:0]=0b11 do not generate interrupt ed15 ed21 ed22 0x007 ed29 0b00 (idle) resume counting due to the extreme strong signal is out of averaging target. cca _rslt maintains until idle/busy detected. ed value>cca_ignore_lvl ed value fedl7344c/e/j-05 ml7344c/e/j 80/154 [ed value 1time idle detection case] set adc_clk_sel ([adc_clk_set: b1 0x08(4)]) =0b1. (1.73 mhz) set ed_avg[2:0] ([ed_ctrl: b0 0x41(2-0)])=0b000. (1 time average) set idle_wait[9:0] ([idle_wait_l/h:b0 0x 3c/3b(1-0)])=0b00 0000 1110 (idle detection 259s) note: *1 digital filter delay is ?ad conversion time * 8?. ad conversion time can be slected by adc_clk_sel ([adc_clk_set: b1 0x08(4)]). reset value is 1.73mhz and ad conversion time is 18.5 s. ed value (internal signal) cca_rslt[1:0] [cca_ctrl: b0 0x39(1-0)] int[18] (cca completion) [int_source_grp3: b0 0x0f(2)] cca_en [cca_ctrl: b0 0x39(4)] ed_value[7:0] [ed_rslt: b0 0x3a] ad conversion (18.5 s) ed value average period (18.5 s) 0b10 (cca on-going) ed1 ed ( 0 ) 0b00 (idle) *1 do not avera g e cca execution period (min.148 s+18.5 s+259 s =425.5 s) < cca_lvl b0 0x37 ed0 ed2 ed13 ed3 ed14 ed ( 1 ) ed ( 2 ) ed ( 12 ) idle_wait[9:0] [idle_wait_l\h: b0 0x3c/3b] idle detection period (259 s) invalid 0x000 0 x 001 0 x 002 0 x 00c (average ed value < cca_lvl) continue for ad conversion period 14 times (259 s), then idle is determined. ed ( 13 ) ed ( 14 ) 0 x 00d 0 x 00e fedl7344c/e/j-05 ml7344c/e/j 81/154 (6) cca threshold setting cca threshold value defined by [cca_lvl: b0 0x37] re gister, should be considered desired input leve (ed value), components variation, temperature fluctuation, loss at antenna and matching circuits. input level and ed value are described in the follow table. rssi value = 1.35 * (input level[dbm] ? variations[dbm] ? other losses[dbm]) + offset ed value (cca threshold) = (rssi value + rssi_adj) * rssi_mag_adj value item high sensitiv ity mode high linearity mode offset 164.5 156 variation (individual, temp.)[dbm] 10 7 other loss[dbm] antenna, matching circuits loss rssi_adj the setting of [rssi_val:b1 0x14] rssi_mag_adj the setting of [rssi_adj: b0 0x66] example) when input level threshold is set to -85dbm conditions: high linearity mode, other loss = 1db, rssi_adj=0, rssi_mag_adj=4.5 rssi value = 1.35 * (-85 - 7 ? 1) + 156 = 30.45 cca threshold = (30.45 + 0) * 4.5 = 137.025 ~ 0x89 in order to validate whether cca threshold is optimised or not, cca should be executed and confirmimg level changing from idle to busy, every time input level is changed, fedl7344c/e/j-05 ml7344c/e/j 82/154 other functions da ta rate setting function (1) data rate change setting ml73444 supports various tx/rx data rate setting defined by the following registers. tx: [tx_rate_h: b1 0x02] and [tx_rate_l: b1 0x03] registers rx: [rx_rate1_h: b1 0x04], [rx_rate1_l: b1 0x05] and [rx_rate2: b1 0x06] registers tx/rx data rate can be defined in the following formula. [tx] tx data rate [bps] = round (26mhz / 13/ tx_rate[11:0]) recommended values for each data rate are in the table below. registers value below are automatically set to [tx_rate_h],[ tx_rate_l] registers by setting tx_drate[3:0] ([drate_set: b0 0x06(3-0)]). tx data rate [kbps] [tx_rate_h][ tx_rate_l] register setting value data rate deviation [%] *1 1.2 1667d -0.02 2.4 833d 0.04 4.8 417d -0.08 9.6 208d 0.16 10.0 200d 0.00 11.52 174d -0.22 15 133d 0.25 *1 data rate deviation is assumption that frequency deviation of master clock(26mhz crystal oscillator or tcxo) is 0ppm. [rx] rx data rate [bps] = round (26mhz / {rx_rate1[11:0] [rx_rate2[6:0]}) recommended values for each data rate are in the table below. registers value below are automatically set to [rx_rate1_h][ rx_rate1_l] [rx_rate2] registers by setting rx_drate[3:0]( [drate_set:b0 0x06(7-4)] ). rx dta rate [kbps] [rx_rate1_h][rx_rate1_l] register setting value [rx_rate2] register setting 1.2 169d 0d 2.4 85d 0d 4.8 42d 0d 9.6 21d 0d 10 11.52 15 note: when low_rate_en([clk_set2:b0 0x03(0)])=0b1, [rx_rate1_h/l] and [rx_rate2] registers are not set automatically by setting rx_drate[3:0]. please calcurate appropriate values by replacing the 8.66mhz to 26mhz in the above formula and set them to each register. fedl7344c/e/j-05 ml7344c/e/j 83/154 (2) other register setting associate with data rate change data rate can be cahnged by rx_drate[3:0] ([drate_set(7-4)]) and tx_drate[3:0] ([drate_set(3-0)]), below registers may have to be changed. note: depending on data rate, the following chage may not be necessary. for details, please refer to each register description. registers parameters name address data rate drate_set b0 0x06 ch_space_h b1 0x23 channel space ch_space_l b1 0x24 gfsk_dev_h b1 0x30 frequency deviation(gfsk) gfsk_dev_l b1 0x31 fsk_dev0_h/gfil0 b1 0x32 fsk_dev0_l/gfil1 b1 0x33 fsk_dev1_h/gfil2 b1 0x34 fsk_dev1_l/gfil3 b1 0x35 fsk_dev2_h/gfil4 b1 0x36 fsk_dev2_l/gfil5 b1 0x37 fsk_dev3_h/gfil6 b1 0x38 fsk_dev3_l b1 0x39 fsk_dev4_h b1 0x3a frequencydeviation (fsk) fsk_dev4_l b1 0x3b fsk_tim_adj4 b1 0x3c fsk_tim_adj3 b1 0x3d fsk_tim_adj2 b1 0x3e fsk_tim_adj1 b1 0x3f frequency deviation time(fsk) fsk_tim_adj0 b1 0x40 iff_adj_h b0 0x5e if adjustment iff_adj_l b0 0x5f demodulator adjustment1 demod_set1 b1 0x57 demodulator adjustment2 demod_set2 b1 0x58 demodulator adjustment3 demod_set3 b1 0x59 demodulator adjustment4 demod_set4 b1 0x5a demodulator adjustment5 demod_set5 b1 0x5b demodulator adjustment6 demod_set6 b1 0x5c demodulator adjustment7 demod_set7 b1 0x5d demodulator adjustment8 demod_set8 b1 0x5e demodulator adjustment9 demod_set9 b1 0x5f fedl7344c/e/j-05 ml7344c/e/j 84/154 interrupt generation function ml7344 support interrupt generation function. when interrupt occurs, interrupt notification signal (sintn) become ?l? to notify interrupt to the host mcu. interrupt elements are divided into the 3 groups, [int_source_grp1: b0 0x0d], [int_source_grp2: b0 0x0e] and [int_source_grp3: b0 0x0f]. each interrupt element can be maskalable using [int_en_grp1: b0 0x10], [int_en_grp2: b0 0x11] and [int_en_grp3: b0 0x12] registers. interrupt notification signal (sintn) can be output from gpio* or ext_clk. for output setting, please refer to [gpio1_ctrl: b0 0x4e], [gpio1_ctrl: b0 0x4f], [gpio2_ctrl: b0 0x50], [gpio3_ctrl: b0 0x51] and [extclk_ctrl: b0 0x52] registers. note: in one of unmask interrupt event occurs, sintn maintains low. (1) interrupt events table each interrupt event is described below table. register interrupt name description int[0] clock stabilization completion interrupt int[1] vco calibration completion interrupt/ int[2] pll unlock interrupt or vco cal request interrupt int[3] rf state transition completion interrupt int[4] fifo-empty interrupt int[5] fifo-full interrupt int[6] wake-up timer completion interrupt int_source_grp1 int[7] clock calibration completion interrupt int[8] rx completion interrupt int[9] crc error interrupt int[10] reserved int[11] rx length error interrupt int[12] rx fifo access error interrupt int[13] syncword detection interrupt int[14] field checking interrupt int_source_grp2 int[15] sync error interrupt int[16] tx completion interrupt int[17] tx data request accept completion interrupt int[18] cca completion interrupt int[19] tx length error interrupt int[20] tx fifo access error interrupt int[21] reserved int[22] general purpose timer 1 interrupt int_source_grp3 int[23] general purpose timer 2 interrupt fedl7344c/e/j-05 ml7344c/e/j 85/154 (2) interrupt generation timing in each interrupt generation, timing from reference point to interrupt generation (notification) are described in the following table. timeout procedure for interrupt notification waiting are also described below. note: (1)the values are described in units of ?bit cycle? in the below table is the value at 100kbps. if using other data rate, please esitimate with appropriate ?bit cycle?. (2)below table uses the following format for tx/rx data. (3)even if each interrupt notification is masked, in case of interrupt occurence, interrupt elements are stored internally. therefore, as soon as interrupt notification is unmasked, interrupt will generate. interrupt notice reference point timing from reference poin t to interrupt generation or interrupt generation timing resetn release (upon power-up) 50 s int[0] clk stabilization completion sleep release (recovered from sleep) 50 s int[1] vco calibration completion vco calibration start 230 s pll unlock detection - (tx) during tx after pa enable. (rx) during rx after rx enable. int[2] vco cal request - (tx) rising edge of pa_on signal. (rx) rising edge of rx enable signal. tx_on command (idle) 1406 s (rx) 1188 s rx_on command (idle) s (tx) 244 s trx_off command (tx) 147 s (rx) 4 s int[3] rf state transition completion force_trx_off command (tx) 147 s (rx) 4 s (tx) tx_on command (*1) nrz coding, empty trigger level is set to 0x02 rf wake-up(1406 s)+ 35 byte (preamble to 22 nd data byte) * 8bit *10(bit cycle) =4206 s int[4] fifo-empty detection (rx) - by fifo read, remaining fifo data is under trigger level (tx) - by fifo write, fifo usage exceed trigger level int[5] fifo-full detection (rx) syncword detection nrz coding, full trigger level is set to 0x05 6byte (length to 5 th data byte) * 8bit * 10 s(bit cycle) = 480 s int[6] wake-up timer completion sleep setting wake-up timer is completed. for details, please refer to ?wake-up timer? int[7] clock calibration completion calibration start calibration timer is completed. for details, please refer to ?low speed clock shift detection function?. (*1) before issuing tx_on, writing full-length tx data to the tx_fifo. 2 byte 10 byte 1 byte 24 byte 2 byte preamble syncword length user data crc fedl7344c/e/j-05 ml7344c/e/j 86/154 interrupt notice reference point timing from reference poin t to interrupt generation or interrupt generation timing int[8] rx completion syncword detection nrz coding, full trigger level is set to 0x05 27byte (length to crc) * 8bit * 10 s(bit cycle) = 2160 s int[9] crc error detection syncword detection (format a/b) each rx crc block calculation completion (format c) rx completion int[10] reserved - - int[11] rx length error detection syncword detection 80 s (l-field 1byte) 160 s (l-field 2byte) int[12] rx fifo access error detection - (1)overflow occurs because fifo read is too slow. (2)underflow occurs because too many fifo data is read int[13] syncword detection - syncword detection int[14] field check completion - match or mismatch detected in field check int[15] sync error detection - during rx after syncword detection, out-of-sync detected. (when rxdio_ctrl[1:0] ([dio_set: b0 0x0c(7-6)]) =0b00 or 0b11.) int[16] tx completion tx_on command (*1) rf wake-up+[tx data+3](bit) after =1406 s+(39byte 10 +3 )bit * 10 s (bit cycle)=4556 s int[17] tx data request accept completion - after full length data are written to the tx fifo. int[18] cca completion cca execution start (1)normal mode (ed value calculation averaging time + idle_wait setting [idle_wait_h/l:b0 0x3b,3c] ) * ad conversion time (2) idle detection mode idle judgment case (ed value calculation averaging time + idle_wait setting [idle_wait_h/l:b0 0x3b,3c] ) * ad conversion time busy judgment case (ed value calculation averaging time) * ad conversion time ad conversion time can be changed by adc_clk_sel ([adc_clk_set:b1 0x08(4)] ). adc conversion time = 14.8 s at 2.17mhz 18.5 s at 1.73mhz for details, please refer to the ?cca (clear channel assessment) function?. int[19] tx length error detection - after set length value to [tx_pkt_len_h/l: b0 0x7a/7b] register int[20] tx fifo access error detection - (1) when the next packet data is written to the tx_fifo before transmitting previous packet data. (2) fifo overflow when writing (3) fifo underflow (no data) when transmitting int[21] reserved - (*1) before issuing tx_on, writing full-length tx data to the tx_fifo. fedl7344c/e/j-05 ml7344c/e/j 87/154 interrupt notice reference point timing from reference poin t to interrupt generation or interrupt generation timing int[22] general purpose timer 1 completion timer start general purpose timer 1 completion general purpose timer clock cycle * division setting [gt_clk_set: b0 0x33] * general purpose timer interval setting [gt1_timer:b0 0x34] for details, please refer to the ?general purpose timer?. int[23] general purpose timer 2 completion timer start general purpose timer 2 completion general purpose timer clock cycle * division setting [gt_clk_set: b0 0x33] * general purpose timer interval setting [gt2_timer:b0 0x35] for details, please refer to the ?general purpose timer?. (3) clearing interrupt condition the following table shows the condition of clearing each intereupt. as a procedure to clear the interrup, it is recommended that the interrupt to be cleared after masking the interrupt. interrupt notification conditions for clearing interrupts int[0] clk stabilization completion after interrupt generated int[1] vco calibration completion after interrupt generated int[2] pll unlock or vco cal request after interrupt generated int[3] rf state transition completion after interrupt generated int[4] fifo-empty after interrupt generated (must clear before next fifo-empty trigger timing) int[5] fifo-full after interrupt generated (must clear before next fifo-full trigger timing) int[6] wake-up timer completion after interrupt generated int[7] clock calibration completion after interrupt generated int[8] rx completion after interrupt generated int[9] crc error after interrupt generated int[10] reserved - int[11] rx length error after interrupt generated int[12] rx fifo access error after interrupt generated int[13] syncword detection after interrupt generated int[14] field checking after interrupt generated int[15] sync error after interrupt generated int[16/] tx completion after interrupt generated int[17] tx data request accept completion after interrupt generated int[18] cca completion after interrupt generated note: clearing interrupt erase cca result as well. int[19] tx length error after interrupt generated int[20] tx fifo access error after interrupt generated int[21] reserved - int[22] general purpose timer 1 after interrupt generated int[23] general purpose timer 2 after interrupt generated fedl7344c/e/j-05 ml7344c/e/j 88/154 low speed clock shift detection function ml7344 has low spleed frequency shift detection function to compensate inaccurate clock generated by rc oscillator (external clock or internal rc oscillation circuits). by detecting frequency shift of the wake up timer, host can set wake-up timer parameters which taking frequency shift into considera tion. more accurate timer operation is possible by adjusting wake-up timer interval setting ([wut_interval_h/l: b0 0x2f/0x30]) or continuous operation timer interv al ([wu_duration: b0 0x31]). setting register frequency shift detection clock frequency setting [clk_cal_set: b0 0x70] clock calibration time [clk_cal_time: b0 0x71] clock calibration result value [clk_cal_h: b0 0x72], [clk_cal_l: b0 0x73] this function is to measure low speed wake-up timer cycle by using accurate high speed internal clock and count result will be stored in [clk_cal_h/l: b0 0x72/0x73] registers. above setting and count numbers are as follows: high speed clock counter = {wakeup timer clock cycle[sleep/wu_set:b0 0x2d(2)] * clcok calibration time setting ([clk_cal_time:b0 0x71(5-0)]) / {master clock cycle (26mhz) / clock division setting value ([clk_cal_set: b0 0x70(7-4)])} clock calibration time is as follows: clock calibration time[s] = wakeup timer clock cycle * clock calibration time setting [example] assuming no division in the internal high speed clock, calibration time is set as 10 cycle and set 1,000 to the wake-up interval timer value. condition: wakeup timer clock frequency = 44khz detection clock division setting clk_cal_div[3:0][clk_cal_set: b0 0x70(7-4)] = 0b0000 clock calibration time setting [clk_cal_time] = 0x0a wake-up interval timert setting [wut_interval_h/l:b0 0x2f,30] = 0x03e8 theoretical high speed clock count = (1/44khz) * 10 / (1/(26/1)mhz) = 5909(0x1715) if getting [clk_cal_h/l:b0 0x72,73] = 0x162e (5678) counter difference = 5678-5909 = -231 frequency shift = 1/{1/44khz + (-231) / 10 * 1 / 26mhz} ? 44khz = 1.79 khz then finding wake-up timer clock frequency accuracy is +4.1% higher. and the compensation vale (c) is calcurared as below: c = wake-up timer interval([wut_interval_h/l:b0 0x2f,30]) * frequecy shift / 44khz = 1000 * 1.79khz / 44khz =41 therefore, setting [wut_interval_h/l:b0 0x2f,30] = 1000+41 =0x0411 to achive more accurate inteval timinig. note: if calibration time is too short or if high speed counter is divided into low speed clock, calibration may not be accurate. fedl7344c/e/j-05 ml7344c/e/j 89/154 antenna switching function (1) antenna switching function by using [2div_ctrl: b0 0x48], [ant_ctrl: b0 0x4c], [spi/ext_pa_ctrl: b0 0x53] registers, tx-rx signal selection (trx_sw), antenna switching signal (ant_sw) can be controlled. ml7344 can support both spdt antena swith control. ant_sw signal and trx_sw signal output considion for each antenna switch are explained below. ant_sw, trx_sw output condition of each idle, tx, rx state are as follow. (default setting) if inv_trx_sw([2div_ctrl: b0 0x48(2)])=0b1, polarity of trx_sw is reversed. inv_trx_sw=0b0 (default setting) inv_trx_sw=0b1 (polarity reverse) tx/rx condition ant_sw trx_sw ant_sw trx_sw description idle l l l h idle state tx l h l l tx state rx l l l h rx state in the above setting, if inv_ant_sw([2div_ctrl: b0 0x48(3)])=0b1, ant_ctrl1([2div_ctrl: b0 0x48(5)])=0b1 are set, polarity of ant_sw pin is reversed. inv_ant_sw=0b0 ant_ctrl1=any (default setting) inv_ant_sw=0b1 ant_ctrl1=0b1 tx/rx state ant_sw trx_sw ant_sw trx_sw description idle l l h l idle state tx l h h h tx state rx l l h l rx state (2) antenna switch forced setting by [ant_ctrl: b0 0x4c] register, ant_sw pin output conditions can be set to fix. tx: by tx_ant_en([ant_ctrl: b0 0x4c(0)])=0b1, tx_ant([ant_ctrl: b0 0x4c(1)]) condition will be output. rx: by rx_ant_en([ant_ctrl: b0 0x4c(4)])=0b1, rx_ant([ant_ctrl: b0 0x4c(5)]) condition will be output. however, output is defined by [gpiio*_ctrl: b0 0x4e - 0x51] register , [gpiio*_ctrl:b0 0x4e - 0x51] registers setting has higer priority. fedl7344c/e/j-05 ml7344c/e/j 90/154 antenna switching control signals can be also used as below. example 1) using spdt switches (note) altenate external pa control signal exsits. (gpiox or ext_clk pin) (note) external circuits around lna_p pin, pa_outpin and antenna switch(spdt) are omitted in this example. spdt lna_p pin pa_out pin lsi a nt_sw output pin (gpiox) fedl7344c/e/j-05 ml7344c/e/j 91/154 lsi adjustment items and adjustment method pa adjustment ml7344e/j have output circuits for 1mw and 20mw (10mw as well) and ml7344c has output circuit for 20mw and 100mw. output circuits can be selected by pa_mode[1:0] ([pa_mode: b0 0x67(5-4)]). output circuit pa_mode[1:0] ml7344e/j ml7344c 0b00 1mw not allowed 0b01 10mw 20mw 0b10 20mw 100mw 0b11 not allowed output power can be adjusted by the following 3 registers. coarse adjustment 1 pa_reg[3:0] ([pa_mode: b0 0x67(3-0)]) 16 resolutions coarse adjustment 2 pa_ adj[3:0] ([pa_adj: b0 0x69(3-0)] ) 16 resolutions fine adjustment pa reg_fine_adj[4:0] ([pa_reg_fine_adj: b0 0x68(4-0)]) 32 resolutions coarse adjustment 1: pa regulator adjustment setting regulator voltage according to the desired output level. however, please set pa regulator voltage to less than [vdd_pa(pin#22) ? 0.3v]. pa_reg[3:0] [pa_mode:b0 0x67] pa regulator voltage [v] 0b0000 1.20 0b0001 1.32 0b0010 1.44 0b0011 1.56 0b0100 1.68 0b0101 1.80 0b0110 1.92 0b0111 2.04 0b1000 2.16 0b1001 2.28 0b1010 2.40 0b1011 2.52 0b1100 2.64 0b1101 2.76 0b1110 2.88 0b1111 3.00 fedl7344c/e/j-05 ml7344c/e/j 92/154 coarse adjustment 2: pa output gain adjustment controlling output power by adjusting pa gain. the typical pa output for pa_adj at 10mw is as follows. 10mw power [dbm] [pa_adj: b0 0x69(3-0)] pa_reg[3:0] =0 pa_reg[3:0] =1 pa_reg[3:0] =2 pa_reg[3:0] =3 pa_reg[3:0] =4 pa_reg[3:0] =5 0 3.8 5.0 5.9 6.3 6.8 7.0 1 4.8 6.2 7.1 7.6 8.2 8.4 2 5.5 6.9 8.0 8.6 9.1 9.5 3 6.1 7.5 8.7 9.4 10.0 10.4 4 6.5 8.0 9.1 9.8 10.5 11.0 5 6.9 8.5 9.6 10.4 11.0 11.5 6 7.2 8.8 9.9 10.8 11.4 12.0 7 7.5 9.1 10.2 11.0 11.8 12.3 8 7.6 9.2 10.3 11.2 11.9 12.4 9 7.8 9.4 10.6 11.4 12.1 12.7 10 8.0 9.6 10.8 11.6 12.5 12.9 11 8.2 9.7 10.9 11.8 12.6 13.1 12 8.3 9.8 11.0 11.9 12.7 13.2 13 8.4 9.9 11.2 12.0 12.8 13.4 14 8.4 10.1 11.3 12.1 13.0 13.5 15 8.6 10.1 11.4 12.3 13.0 13.6 fine adjustment : pa regulator voltage fine adjustment fine tuning output power by adjusting pa regulator voltage. adjustment step is less than 0.2db. however, please set pa regulator voltage to less than [vdd_pa(pin#22) ? 0.3v]. fedl7344c/e/j-05 ml7344c/e/j 93/154 pa_reg_fine_adj[4:0] [pa_reg_fine_adj:b0 0x68] pa regulator voltage [v] 0b0_0000 89.5% 0b0_0001 90.1% 0b0_0010 90.7% 0b0_0011 91.3% 0b0_0100 91.9% 0b0_0101 92.5% 0b0_0110 93.2% 0b0_0111 93.8% 0b0_1000 94.4% 0b0_1001 95.1% 0b0_1010 95.8% 0b0_1011 96.5% 0b0_1100 97.1% 0b0_1101 97.8% 0b0_1110 98.6% 0b0_1111 99.3% 0b1_0000 100.0% 0b1_0001 100.7% 0b1_0010 101.5% 0b1_0011 102.3% 0b1_0100 103.0% 0b1_0101 103.8% 0b1_0110 104.6% 0b1_0111 105.4% 0b1_1000 106.3% 0b1_1001 107.1% 0b1_1010 107.9% 0b1_1011 108.8% 0b1_1100 109.7% 0b1_1101 110.6% 0b1_1110 111.5% 0b1_1111 112.4% note: in order to achieve the most optimized result, matching circuits may vary depending on the output mode. fedl7344c/e/j-05 ml7344c/e/j 94/154 pa output adjustment flow start end coarse adjustment 1: pa_mode setting and p a regulator adjustment [pa_mode: b0 0x67] coarse adjustment 2: pa output gain adjustment pa output gain adjustment [pa_adj: b0 0x69] fine adjustment: pa regulator fine adjustment [pa_reg_fine_adj: b0 0x68] fedl7344c/e/j-05 ml7344c/e/j 95/154 i/q adjustment image rejection ratio can be adjusted by tuning iq si gnal balance. the adjustment procedure is as follows: 1. from sg, image frequency signal is input to ant pin (#24). input signal: no modulation wave input frequency: channel frequency - (2 * if frequency) if frequency = 200khz: input level: -70dbm 2. isuuing rx_on by [rf_status:b0 0x0b] register, by adjusting z [lo_bias_ip: b2 0x2c] from 0x50 to 0xd0 step 0x04 z [lo_bias_in: b2 0x2d] from 0x60 to 0xa0 step 0x10 z [lo_bias_qp: b2 0x2e] from 0x50 to 0xd0 step 0x04 z [lo_bias_qn: b2 0x2f] from 0x60 to 0xa0 step 0x10 , finding setting value so that ed value [ed_rslt: b0 0x3a] is minimum. 3. it is possible to choice the adjusted value and break the above search flow at halfway. to obtain minimum 30db blocking characteristic for image frequency, ml7344 requires more than 40db attenuation for image frequency (imrr: image rejection ratio). the 10db differ is caused by co-channel blocking characteristic of ml7344. becau se input -70dbm signal during iq adjustment, imrr is more than 40db if ml7344 indicates less than -110dbm by ed value. it is possible to break adjustment flow at halfway by using the ed value as ?target value? in the iq adjustment flow. iq adjustment flow for iq adjustment, using bank2 (closed bank) registers. any other register access is inhibited. 1 read ed value [ed_rslt: b0 0x3a] iq bias initializing setting [lo_bias_in: b2 0x2d] = 0x80 [lo_bias_qn:b2 0x2f] = 0x80 start power on sg output setting modulation: no modulation level : -70dbm frequency: ch frequency- 2 * if frequency initialize setting * please refer to ?initialization table?. rx_on setting [rf_status: b0 0x0b] 1 iq adjustment by following register [lo_bias_ip: b2 0x2c] [lo_bias_qp:b2 0x2e] read ed value < target value ? change setting value of [lo_bias_in: b2 0x2c] [lo_bias_qn:b2 0x2e] no fedl7344c/e/j-05 ml7344c/e/j 96/154 vco adjustment in order to compensate vco operation margin, optimi zed capacitance compensation value should be set in each tx/rx operation and frequency. this capacita nce compensation value can be acquired by vco calibration. by performing vco calibration when power-up or reset, acquired capacitance compensation values for upper limit and lower limit of operation frequency range (for both tx/rx), based on this value optimised capacitance value is applied during tx/rx operation. vco adjustment flow the following flow is the procedure for acquiring cap acitance compensation value when power-up or reset. note:1) vco calibration should be performed only during idle state. end y es start end setting low limit frequency [vco_cal_min_i: b1 0x4d] [vco_cal_min_fh: b1 0x4e] [vco_cal_min_fm: b1 0x4f] [vco_cal_min_fl: b1 0x50] setting operation frequency range [vco_cal_max_n: b1 0x51] initialize setting v co calibration completion int. clear int[1] ( [int_source_grp1: b0 0x0d]) set v co_cal_start = 0b1 [vco_cal_start: b0 0x6f(0)] start calibration calibration operation completion wait v co calibration completion int? int[1] [int_source_grp1: b0 0x0d] no y es fedl7344c/e/j-05 ml7344c/e/j 97/154 vco calibration is necessary every 2.6ms to 8.8ms. after completion, capacitance compensation values are stored in the following registers. capacitance compensation value at tx low limit frequency: [txvcal_min: b1 0x52] capacitance compensation value at tx upper limit frequency: [txvcal_max: b1 0x53] capacitance compensation value at rx low limit frequency: [rxvcal_min: b1 0x54] capacitance compensation value at rx upper limit frequency: [rxvcal_max: b1 0x55] fedl7344c/e/j-05 ml7344c/e/j 98/154 in actual operation, based on the 2 compensation values for each tx/rx, the most optimized capacitance value for the frequency is calculated and applied. the calculated value is stored in [vco_cal: b0 0x6e]. by evaluation stage, if below values are stored in the mcu memory and uses these values upon reset or power-up, calibration operation can be omitted. registers to be saved in the mcu memory. [vco_cal_min_i: b1 0x4d] [vco_cal_min_fh: b1 0x4e] [vco_cal_min_fm: b1 0x4f] [vco_cal_min_fl: b1 0x50] [vco_cal_max_n: b1 0x51] [txvcal_min: b1 0x52] [txvcal_max: b1 0x53] [rxvcal_min: b1 0x54] [rxvcal_max: b1 0x55] after issuing vco calibration, vco tuning voltage may be out of control range by the temperature difference between operating timing and vco calibration timing. if activating rf when vco tuninng voltage is out of control range, the margine of vco operation will be lost and it may cause the pll unlock. when detecting vco tuning voltage is out of control range, vco calibration should be re-issued or set vco caluibration value which has operating margine at that temperature. the ml7344 has the function of comparing the vco tunign voltage with upper and lower limit voltages and determining it is in the control range or not and indiacting the result. after detecting vco tuning voltage is out of contol range, it can be notified by int[2] (group1: vco cal request interrupt). [relative controlo bit] the comparison result with maximum threshold: vtune_comp_h ([vco_vtrslt:b0 0x40(1)]) the comparison result with minimum threshold: vtune_comp_l ([vco_vtrslt:b0 0x40(0)]) vco cal request interrupt enable setting: vtune_int_enb ([vco_vtrslt:b0 0x40(2)]) state control after pll unlock detection: pll_ld_en ([pll_lock_detect:b1 0x0b(7)] [vco voltage condition] vtune_comp_l [vco_vtrslt:b0 0x40(0)] vtune_comp_h [vco_vtrslt:b0 0x40(1)] condition 0b0 0b0 ordinary 0b0 0b1 out of control range (beyond upper level) 0b1 0b0 out of control range (below lower level) 0b1 0b1 extra ordinary note: 1. for low limit frequency, please use frequency at least 400khz lower than operation frequency 2. for upper limit frequency should be selected so th at operation frequency is in the frequency range. 3. in case of like a channel change, if the setting frequency is outside of calibration frequency range, calibration process has to be performed again with proper frequency. 4. int[2] (group1) will generate by detecting pll unlock or vco cal request (when vtune_int_enb ([vco_vtrslt:b0 0x40(2)])=0b1). the following shows the ml7344 opereation related with lsi state and pll_ld_en([pll_lock_detect:b1 0x0b(7)]) setting, after interrupt generation. fedl7344c/e/j-05 ml7344c/e/j 99/154 [in case of pll unlock interrupt] pll lock detection control setting and ml 7344 operation after interrupt generation lsi state check timig of pll unlock detection pll_ld_en=0b1 [pll_lock_detect:b1 0x0b(7)] pll_ld_en=0b0 [pll_lock_detect:b1 0x0b(7)] tx pa_on =?h? interrupt occurs and tx stops forcibly interrupt occurs and tx is continued rx rx enable =?h? interrupt occurs and rx is continued interrupt occurs and rx is continued [in case of vco cal request interrupt] pll lock detection control setting and ml 7344 operation after interrupt generation lsi state check timig of pll unlock detection pll_ld_en=0b1 [pll_lock_detect:b1 0x0b(7)] pll_ld_en=0b0 [pll_lock_detect:b1 0x0b(7)] tx rising edge of pa_on signal interrupt occurs and tx stops forcibly interrupt occurs and tx is continued rx rising edhe of rx enable signal interrupt occurs and rx is continued interrupt occurs and rx is continued fedl7344c/e/j-05 ml7344c/e/j 100/154 vco low limit frequency setting vco low limit frequency can be set as described in the ?channel frequency setting?. i is set to [vco_cal_min_i:b1 0x4d] register, f is set to [vco_cal_min_fh:b1 0x4e], [vco_cal_min_fm:b1 0x4f], [vco_cal_min_fl:b1 0x50] in msb ? lsb order. example) if operation low limit frequency is 426.6mhz, setting value should be lower than 400khz. then in following example, low limit frequency is set to 426.mhz, master clock frequency is 26mhz. i = 426mhz/26mhz (integer part) = 16(0x10) f =(426mhz/26mhz-16) * 2 20 (integer part) = 403298 (0x062762) setting values for each register is as follows: [vco_cal_min_i] = 0x10 [vco_cal_min_fh] = 0x06 [vco_cal_min_fm] = 0x27 [vco_cal_min_fl] = 0x62 vco upper limit frequency setting vco upper limit frequency is calculated as following formula, based on low limit frequency values and [vco_cal_max_n:b1 0x51] register. vco calibration upper limit frequency = vco calibration low limit frequency (b1 0x4d-0x50) + f(b1 0x51) f is defined in the table below vco_cal_max_n[3:0] ? f[mhz] 0b0000 0 0b0001 0.8125 0b0010 1.625 0b0011 3.25 0b0100 6.5 0b0101 13 0b0110 26 0b0111 52 0b1000 82.875 0b1001 104 other than above prohibited fedl7344c/e/j-05 ml7344c/e/j 101/154 energy detection value (ed value) adjustment ed value is calculated by rssi signal (analog signal) from rf part, by performing the following adjustment, it is possible to correct the variation in lsis. [ed value] ed value is calculated as following formula, rssi value = 1.35 * (input level[dbm] ? variations[dbm] ? other losses[dbm]) + offset ed value (cca threshold) = (rssi value + rssi_adj) * rssi_mag_adj value item high sensitiv ity mode high linearity mode offset 164.5 156 variation (individual, temp.)[dbm] 10 7 other loss[dbm] antenna, matching circuits loss rssi_adj the setting of [rssi_val:b1 0x14] rssi_mag_adj the setting of [rssi_adj: b0 0x66] [ed value asjustment] at first, inputting the low-level signal to ant terminal. adjusting the rssi_adj value so that ed_value [ed_rslt:b0 0x3a(7-0)] indicates the target value of the low-level signal.. next inputting the high-level signal and adjusting the rssi_mag_adj value so that ed_value indicates the target value of the high-level signal. repeat several times in accordance with the required accuracy. ed value rssi_adj (b0 0x66) rssi_mag_adj (b1 0x13) rf input level high low- fedl7344c/e/j-05 ml7344c/e/j 102/154 oscillation circuit adjustment in case of using a crystal oscillator (ml7344xc), crystal oscillator frequency deviation can be tuned by adjusting load capacitance of xin pin (pin#5) and xout pin (pin #6). load capacitance can be adjusted by [osc_adj1: b0 0x62] and [osc_adj2: b0 0x63]. adjustable capacitance is as follows: [osc_adj1] coarse adjustment of load capacitance: 0.7pf/step (setting range: 0x00 to 0x0f) [osc_adj2] fine adjustment of load capacitance: 0.02pf/step (setting range: 0x00 to 0x77) osc_adj oscillating frequency fedl7344c/e/j-05 ml7344c/e/j 103/154 resister setting initialization table ml7344 needs initilaization. for the value to each regi ster, please refer to the ?ml7344 initilaization table? document. rx mode setting ml7344 has two rx modes. one is ?high sensitivity mode? that is tuned for minimum rx sensitivity. it achieves -118dbm under condition of ber<0.1%, 4.8kbps and fdev=3khz. the other is ?high linearity mode? that improves linearity about 6db, so characteristics of blocking and power detection rang are grown instead of sensitivity degradation about 3db. for swtiching rx mode, set the register [lna_gain1:b2 0x28] as below. rx mode [lna_gain1:b2 0x28] high sensitivity mode 0xf7 high linearity mode 0x07 ber measurement setting the following registers setting are necessary for rx side when measuring ber. [dio_set: b0 0x0c] = 0x40 [mon_ctrl: b0 0x4d] = 0x80 [gpio0_ctrl: b0 0x4f] to [gpio3_ctrl: b0 0x52] for setting dclk/dio output pins. [gain_htom: b1 0x0e] = 0x1e when termiate ber measurement and reurn from rx state, force trx_off should be issued by set_trx[3:0] ([rf_status:b0 0x0b(3-0]) =0b0011. wireless m-bus setting the following parameter tables are example fo r programing each wireless m-bus mode (n/f). mode n (channel frequency: 169.4125mhz, modulation: gfsk, data rate: 4800bps) register parameter name address setting value txfreq_i b1 0x1b 0x0d txfreq_fh b1 0x1c 0x00 txfreq_fm b1 0x1d 0x81 tx frequency txfreq_fl b1 0x1e 0xf8 rxfreq_i b1 0x1f 0x0d rxfreq_fh b1 0x20 0x00 rxfreq_fm b1 0x21 0x81 rx frequency rxfreq_fl b1 0x22 0xf8 ch_space_h b1 0x23 0x07 channel space ch_space_l b1 0x24 0xe0 pll frequency division pll_div_set b1 0x1a 0x10 fedl7344c/e/j-05 ml7344c/e/j 104/154 data rate drate_set b0 0x06 0x22 data_set1 b0 0x07 0x10 tx\rx data configulation data_set2 b0 0x08 0x00 gfsk_dev_h b1 0x30 0x00 frequency deviation (gfsk) gfsk_dev_l b1 0x31 0x60 fedl7344c/e/j-05 ml7344c/e/j 105/154 mode n setting (continued) register parameter name address setting value fsk_dev0_h/gfil0 b1 0x32 0x49 fsk_dev0_l/gfil1 b1 0x33 0xa7 fsk_dev1_h/gfil2 b1 0x34 0x0f fsk_dev1_l/gfil3 b1 0x35 0x14 fsk_dev2_h/gfil4 b1 0x36 0x19 fsk_dev2_l/gfil5 b1 0x37 0x1d fsk_dev3_h/gfil6 b1 0x38 0x1e fsk_dev3_l b1 0x39 - fsk_dev4_h b1 0x3a - frequency deviation (fsk) fsk_dev4_l b1 0x3b - fsk_tim_adj0 b1 0x3c - fsk_tim_adj1 b1 0x3d - fsk_tim_adj2 b1 0x3e - fsk_tim_adj3 b1 0x3f - frequency deviation time fsk_tim_adj4 b1 0x40 - txpr_len_h b0 0x42 0x00 preamble length txpr_len_l b0 0x43 0x08 syncword length sync_word_len b1 0x25 0x10 sync_word1_set0 b1 0x27 0x00 sync_word1_set1 b1 0x28 0x00 sync_word1_set2 b1 0x29 0xf6 syncword pattern 1 sync_word1_set3 b1 0x2a 0x8d sync_word2_set0 b1 0x2b - sync_word2_set1 b1 0x2c - sync_word2_set2 b1 0x2d - syncword pattern 2 sync_word2_set3 b1 0x2e - postamble setting postamble_set b0 0x44 0x00 iff_adj_h b0 0x5e 0x00 demodulator dc level iff_adj_l b0 0x5f 0x00 demodulator adjustment 1 demod_set1 b1 0x57 t.b.d. demodulator adjustment 2 demod_set2 b1 0x58 t.b.d. demodulator adjustment 3 demod_set3 b1 0x59 t.b.d. demodulator adjustment 4 demod_set4 b1 0x5a t.b.d. demodulator adjustment 5 demod_set5 b1 0x5b t.b.d. demodulator adjustment 6 demod_set6 b1 0x5c t.b.d. demodulator adjustment 7 demod_set7 b1 0x5d t.b.d. demodulator adjustment 8 demod_set8 b1 0x5e t.b.d. demodulator adjustment 9 demod_set9 b1 0x5f t.b.d. fedl7344c/e/j-05 ml7344c/e/j 106/154 mode f register parameter name address setting value txfreq_i b1 0x1b 0x10 txfreq_fh b1 0x1c 0x0a txfreq_fm b1 0x1d 0xf7 tx frequency txfreq_fl b1 0x1e 0x55 rxfreq_i b1 0x1f 0x10 rxfreq_fh b1 0x20 0x0a rxfreq_fm b1 0x21 0xf7 rx frequency rxfreq_fl b1 0x22 0x55 ch_space_h b1 0x23 - channel space ch_space_l b1 0x24 - pll frequency division pll_div_set b1 0x1a 0x00 data rate drate_set b0 0x06 0x11 data_set1 b0 0x07 0x00 tx\rx data configulation data_set2 b0 0x08 0x00 gfsk_dev_h b1 0x30 - frequency deviation (gfsk) gfsk_dev_l b1 0x31 - fsk_dev0_h/gfil0 b1 0x32 0x00 fsk_dev0_l/gfil1 b1 0x33 0x44 fsk_dev1_h/gfil2 b1 0x34 0x00 fsk_dev1_l/gfil3 b1 0x35 0x82 fsk_dev2_h/gfil4 b1 0x36 0x00 fsk_dev2_l/gfil5 b1 0x37 0xb3 fsk_dev3_h/gfil6 b1 0x38 0x00 fsk_dev3_l b1 0x39 0xd2 fsk_dev4_h b1 0x3a 0x00 frequency deviation (fsk) fsk_dev4_l b1 0x3b 0xd0 fsk_tim_adj0 b1 0x3c 0x7f fsk_tim_adj1 b1 0x3d 0x7f fsk_tim_adj2 b1 0x3e 0x7f fsk_tim_adj3 b1 0x3f 0x7f frequency deviation time fsk_tim_adj4 b1 0x40 0x7f txpr_len_h b0 0x42 0x00 preamble length txpr_len_l b0 0x43 0x27 syncword length sync_word_len b1 0x25 0x10 sync_word1_set0 b1 0x27 0x00 sync_word1_set1 b1 0x28 0x00 sync_word1_set2 b1 0x29 0xf6 syncword pattern 1 sync_word1_set3 b1 0x2a 0x8d sync_word2_set0 b1 0x2b 0x00 sync_word2_set1 b1 0x2c 0x00 sync_word2_set2 b1 0x2d 0xf6 syncword pattern 2 sync_word2_set3 b1 0x2e 0x72 postamble setting postamble_set b0 0x44 0x00 fedl7344c/e/j-05 ml7344c/e/j 107/154 mode f setting (continued) register parameter name address setting value iff_adj_h b0 0x5e 0x00 demodulator dc level iff_adj_l b0 0x5f 0x00 demodulator adjustment 1 demod_set1 b1 0x57 t.b.d. demodulator adjustment 2 demod_set2 b1 0x58 t.b.d. demodulator adjustment 3 demod_set3 b1 0x59 t.b.d. demodulator adjustment 4 demod_set4 b1 0x5a t.b.d. demodulator adjustment 5 demod_set5 b1 0x5b t.b.d. demodulator adjustment 6 demod_set6 b1 0x5c t.b.d. demodulator adjustment 7 demod_set7 b1 0x5d t.b.d. demodulator adjustment 8 demod_set8 b1 0x5e t.b.d. demodulator adjustment 9 demod_set9 b1 0x5f t.b.d. fedl7344c/e/j-05 ml7344c/e/j 108/154 flowcharts category condition 1 condition 2 name of flow turn on sequence - - (1) initialization flow tx/rx common sequence - - (1) rf state transition wait dio mode - tx (1) dio mode under 64 byte tx (2) fifo mode fifo mode 65 byte or more (fast_tx) tx (3) fifo mode tx sequence automatic tx - tx (4) automatic tx dio mode - rx (1) dio mode under 64 byte rx (2) fifo mode fifo mode 65 byte or mode rx (3) fifo mode ack transmission - rx (4) ack transmission field check - rx (5) field checking normal mode rx (6) cca normal mode continuous execution mode rx (6) cca continuous execution mode cca idle detection mode rx (6) cca idle detection mode high speed carrier checking - rx (7) high speed carrier checking rx sequence ed-scan - rx (8) ed-scan sleep - (1) sleep sleep sequence wake-up timer - (2) wake-up timer sync error - (1) sync error tx fifo access error - (2) tx fifo access error rx fifo access error - (3) rx fifo access error error process pll unlock - (4) pll unlock data rate change process - - (1) change data rate fedl7344c/e/j-05 ml7344c/e/j 109/154 turn on sequence (1) initialization flow in initialization status, interrupt process, registers setting, vco calibration are necessary. (1) interrupt process upon reset, all interrupt notification settings ([int_en_grp1-3: b0 0x10- 0x12]) are disabled. after hard reset is released, int[0] (group 1: cl ock stabilization completion interrupt) will be detected. int[0] should be enabled by [int_en_grp1:b0 0x10] register. (2) registers setting after hard reset is released, all registers in bank0 and bank1 except fifo access registers ([wr_tx_fifo: b0 0x7c] and [rd_fifo: b0 0x7f ]), are accessible before int[0] notification. (3) vco calibration vco calibration is executed after setting upper and low limit of the operation frequency. for details, please refer to the ?vco adjustment?. register setting start clock stabilized completion int. ? int[0] [int_source_grp1: b0 0x0d] yes n o end int[0] clear [int_source_grp1 b0 0x0d] (2)register setting (1)interrupt process vco calibration execution int_en setting [int_en_grp1-3: b0 0x10-0x12] (3)vco calibration *for details, please refer to the ?vco adjustment? fedl7344c/e/j-05 ml7344c/e/j 110/154 tx/rx common sequence (1) rf state transition wait if below setting for rf state change is selected, please confirm the completion of rf state transtion by int[3] (group1: rf state transtion completion interrupt). rf state transition by [rf_status: b0 0x0b] register rf state transition by [rf_status_ctrl: b0 0x0a] resgister fast_tx mode setting automatic tx setting rf state setting after tx completion rf state setting after rx completion rf state modification by wake-up timer setting i) trx_off flow rf state change by [rf_status: b0 0x0b] set_trx[3:0]=0b1000 rf state change by [rf_status_ctrl: b0 0x0a] txdone_mode[1:0=0b00 rxdone_mode[1:0]=0b00 start trx_off issue [rf_status: b0 0x0b] end rf state transition completion interrupt confirmation int[3]([int_source_grp1: b0 0x0d] start end rf state transition completion interrupt confirmation int[3] [int_source_grp1: b0 0x0d] tx completion interrupt? int[16] [int_source_grp3: b0 0x0f] yes n o start end rf state transition completion interrupt confirmation int[3] [int_source_grp1: b0 0x0d] tx completion interrupt? int[8] [int_source_grp2: b0 0x0e] yes n o fedl7344c/e/j-05 ml7344c/e/j 111/154 ii) tx_on flow rf state transition change by [rf_status: b0 0x0b] set_trx[3:0]=0b1001 rf state transition by [rf_status_ctrl]register(b0 0x0a) rxdone_mode[1:0]=0b10 fast_tx_en=0b1 and auto_tx_en=0b1 start tx_on issue [rf_status: b0 0x0b] end rf state transition completion interrupt confirmation int[3] [int_source_grp1: b0 0x0d] start end rf state transition completion interrupt confirmation int[3] [int_source_grp1: b0 0x0d] rx completion int.? int[8] [int_source_grp2: b0 0x0e] yes n o start fifo write end rf state transition completion interrupt confirmation int[3] [int_source_grp1: b0 0x0d] fedl7344c/e/j-05 ml7344c/e/j 112/154 iii) rx_on flow rf state change by [rf_status: b0 0x0b] rf state change by [rf_status_ctrl: b0 0x0a] set_trx[3:0]=0b0110 txdone_mode[1:0]=0b10 iv) wake-up flow the following flow doses not apply to the case when waiting for int[14] (group 1: field checking interrupt) after wake-up. start rx_on issue [rf_status: b0x0b] end start end sleep setting rf state transition completion interrupt confirmation int[3] [int_source_grp1: b0 0x0d] start end tx completion int ? int[16] ([[int_source_grp2: b0 0x0f]] yes n o rf state transition completion interrupt confirmation int[3] [int_source_grp1: b0 0x0d] rf state transition completion interrupt confirmation int[3] [int_source_grp1: b0 0x0d] fedl7344c/e/j-05 ml7344c/e/j 113/154 tx sequence (1) dio mode dio(tx) mode can be selected by setting txdio_ctrl[1:0]([dio_set: b0 0x0c(5-4)])=0b01 or 0b10. in dio mode, when tx_on is issued, data input on the pin related dio will be transimitted to the air. after tx completion, trx_off should be issued. *3: timing up to dclk output varies depending on tx preamble, sfc, data rate. *2: preamble/syncword is transmitted based on the following registers. preamble [data_set1: b0 0x07] [txpr_len_h/l: b0 0x42-43] syncword [syncword1_set0-3: b1 0x27-2a] [syncword2_set0-3: b1 0x2b-2e] [sync_word_len: b1 0x25] [data_set2: b0 0x08] *4: tx data must be input at falling edge of dclk. *1 dio/dclk pins are defined as follows: [gpio0_ctrl: b0 0x4e] [gpio1_ctrl: b0 0x4f] [gpio2_ctrl: b0 0x50] [gpio3_ctrl: b0 0x51] [ext_clk_ctrl: b0 0x52] [spi/ext_pa_ctrl: b0 0x53] *5: please refer to rf state transition wait flow. preamble/syncword setting *2 start tx_on issue [rf_status: b0 0x0b] end n o tx completed?*5 yes trx_off issue [rf_status: b0 0x0b] tx data input *4 (dio pins) yes next packet to be transmitted? n o txdio_ctrl setting=0b10 [dio_set: b0 0x0c(5-4)] dio pins setting *1 dclk output wait *3 fedl7344c/e/j-05 ml7344c/e/j 114/154 (2) fifo mode (less than 64 byte) fifo mode (packet mode) can be selected by setting txdio_ctrl[1:0]([dio_set: b0 0x0c(5-4)])=0b00. in fifo mode, data is written to the tx_fifo by [wr_tx_fifo:b0 0x7c] register. after writing full data of a packet, issuing tx_on by [rf_status:b0 0x0b] resister. following preamble/syncword, tx_fifo data is transmitted to the air. upon tx completion interrupt (int[16] group 3) occurs, interrupt must be cleared. if the next tx packet is sent, the next tx packet data is written to the tx_fifo. if rx is expected after tx, rx_on should be issued by [rf_status: b0 0x0b] resister. tx can be terminated by issuing trx_off by [rf_status:b0 0x0b] register. start write tx data [wr_tx_fifo:b0 0x7c] tx_on issue [ rf status: b0 0x0b ] tx completion (int[16])? [int_source_grp3: b0 0x0f(0)] n o yes n o int[16] clear [int_source_grp3: b0 0x0f]) next packet tx ? yes trx_off issue [rf_status: b0 0x0b] write tx data [wr_tx_fifo:b0 0x7c] rx? n o rx_on issue [rf_status: b0 0x0b] yes tx_fifo trigger level setting [txfifo_thrh: b0 0x17]=0x00 [txfifo_thrl: b0 0x18]=0x00 tx data request accept completion (int[17])? [int_source_grp3: b0 0x0f(1)] n o n o cca execution ? to cca flowchart i) if random back-off period specified i n the ieee is used, go to cca normal mode. ii) if idle is detected in minimum period, go to cca idle detection mode. yes set rx_on after tx completion? [rf_status_ctrl:b0 0x0a] yes yes n o if the tx data length is shorter than the fast_tx trigger level, tx will start b y writing all data to fifo. set trx_off/sleep after tx? [rf_status_ctrl:b0 0x0a] yes n o please refer to rf state transition wait flow. to rf state transition wai t flo w int[17] clear [ int source grp3: b0 0x0f ] cca result=busy? from cca flowchart cca continue? yes trx_off issue [ rf _ status: b0 0x0b ] tx fifo clear [ state clr: b0 0x16 ] n o n o to rf state transition wai t flow yes to rf state transition wait flow to rf state transition wai t and rx flow fedl7344c/e/j-05 ml7344c/e/j 115/154 (3) fifo mode (65 byte or more) the host must write tx data to the tx_fifo while checking int[5] (group1: fifo-full interrupt) and int[4] (group1: fifo-empty interrupt) in order to avoid fifo-overrun or fifo-underrun. other operations are identical to the fifo mode (less than 64byte). enabling fast_tx mode by fast_tx_en ([rf_status_ctrl: b0 0x0a(5)] =0b1, tx will start when data amount written to the fifo exceeds the bytes+1 in the [txfifo_thrl: b0 0x18]. n o yes n o n o yes if data written to fifo exceed thfifo_thrl[5:0] ([txfifo_thrl:b0 0x18(5-0)] +1, tx will start. please refer to rf state transition wait flow. fifo-empty (int[4]) ? [int_source_grp1: b0 0x0d(4)] fast_tx mode setting [rf_status_ctrl: b0 0x0a] tx fifo-full level setting [txfifo_thrh: b0 0x17] tx fifo-empty level setting [txfifo_thrl: b0 0x18] int[4] clear [int_source_grp: b0 0x0d] .total data amount should be identical to the length. length data is (length ? crc size). if tx data written exceed the length, after tx completion interrupt, tx fifo must be cleared by issuing trx_off. yes tx fifo-empty level disable setting [tx_fifo_thrl: b0 0x18] tx fifo-empty level enable setting [tx_fifo_thrl: b0 0x18] start write tx data [wr_tx_fifo:b0 0x7c] write tx data [wr_tx_fifo:b0 0x7c] tx data request accept completion (int[17])? [int_source_grp3: b0 0x0f(1)] tx completion (int[16])? [int_source_grp3: b0 0x0f(0)] n o int[16] and int[17] clear [int_source_grp3: b0 0x0f]) next packet tx ? yes trx_off issue [rf_status: b0 0x0b] write tx data [wr_tx_fifo:b0 0x7c] rx? n o rx_on issue [rf_status: b0 0x0b] yes set rx_on after tx completion? [rf_status_ctrl:b0 0x0a] yes n o set trx_off/sleep after tx? [rf_status_ctrl:b0 0x0a] yes n o to rf state transition wait flo w to rf state transition wait flow to rf state transition wai t and rx flow fedl7344c/e/j-05 ml7344c/e/j 116/154 (4) automatic tx (less than 64 byte) if auto_tx_en([rf_status_ctrl: b0 0x0a(4)]=0b1, tx starts automatically when fifo is filled with data equivalent to the langth. afer tx completion, rfstate transition setting is by txdone_mode ([rf_status_ctrl: b0 0x0a(1-0)]). start write tx data [wr_tx_fifo:b0 0x7c] automatic tx setting [rf_status_ctrl:b0 0x0a] tx data request accept completion (int[17])? [int_source_grp3: b0 0x0f(1)] n o yes tx completion (int[16])? [int_source_grp3: b0 0x0f(0)] n o yes n o int[16] and [int17] clear [int_source_grp3: b0 0x0f]) next packet tx ? yes trx_off issue [rf_status: b0 0x0b] write tx data [wr_tx_fifo:b0 0x7c] rx? n o rx_on issue [rf_status: b0 0x0b] yes set rxon after tx completion? [rf_status_ctrl:b0 0x0a] yes n o set trxoff/sleep after tx? [rf_status_ctrl:b0 0x0a] yes n o to rf state transition wai t flo w to rf state transition wait flow to rf state transition wai t and rx flow when data equivalent to length is written to fifo, tx starts automatically. please refer to rf state transition wait flow. fedl7344c/e/j-05 ml7344c/e/j 117/154 rx sequence (1) dio mode dio mode can be selected by setting rxdio_ctrl[1:0]([dio_set: b0 0x0c(7-6)])=0b10/0b11. upon setting dio mode and issuing rx_on by [rf_status:b0 0x0b] register, syncword detection will be started. dio output mode 1 operation when rxdio_ctrl[1:0]=0b10 setting, after syncword patte rn detection, rx data will be strored into the rx_fifo. rx data stored in the rx_fifo is output through dio pins, if setting dio_start ([dio_set: b0 0x0c(0)])=0b1. after rx completion, if more data is to be received, by setting dio_rx_complete ([dio_set: b0 0x0c(2)]) =0b1 (dio rx completion), the next packet will be ready to receive. in case of trx_off, issuing trx_off by [rf_status:b0 0x0b] register. *3: please refer to rf state transition wait flow *2: preamble, syncword and error tolerance are set by following registers. preamble [data_set1: b0 0x07] [sync_condition1-3: b0 0x45-47] syncword [syncword1_set0-3: b1 0x27-2a] [syncword2_set0-3: b1 0x2b-2e] [sync_word_len: b1 0x25] [data_set2: b0 0x08] *5 rx data must be transferred to the host at risin g ed g e of dcl k . *1 dio/dclk pins are defined as follows: [gpio0_ctrl: b0 0x4e] [gpio1_ctrl: b0 0x4f] [gpio2_ctrl: b0 0x50] [gpio3_ctrl: b0 0x51] [ext_clk_ctrl: b0 0x52] [spi/ext_pa_ctrl: b0 0x53] preamble/syncword error tolerance setting *2 start rx_on issue *3 [rf_status: b0 0x0b] n o rx completed? yes trx_off issue [rf_status: b0 0x0b] read rx data *5 (dio pins) yes next packet to be rx? rxdio_ctrl setting=0b10 [dio_set: b0 0x0c(7-6)] dio pins setting *1 dio_start =0b1 [dio_set:0b 0x0c(0)] n o yes syncword detection (int[13])? [int_source_grp3: b0 0x0f(5)] n o to rf state transition wait flow dio_rx_completion=0b1 [dio_set: b0 0x0c(2)] dclk output? (dclk function pin) n o yes wait *4 *4 wait time should be more than 1 byte dat a receivin g p eriod fedl7344c/e/j-05 ml7344c/e/j 118/154 dio output mode 2 operation while rxdio_ctrl[1:0]=0b11, rx data (after l-field) will be stored into the rx_fifo. rx data stored in the rx_fifo is output through dio pins, if setting dio_start ([dio_set: b0 0x0c(0)])=0b1. upon outputting rx data defined by l-field, rx is completed and generate rf completion interrupt (int[8] group2). in case of trx_off, issuing trx_off by [rf_status:b0 0x0b] register. *3: please refer to rf state transition wait flow *2: preamble, syncword and error tolerance are set by following registers. preamble [data_set1: b0 0x07] [sync_condition1-3: b0 0x45-47] syncword [syncword1_set0-3: b1 0x27-2a] [syncword2_set0-3: b1 0x2b-2e] [sync_word_len: b1 0x25] [data_set2: b0 0x08] *5 rx data must be transferred to the host at rising edge of dclk. *1 dio/dclk pins are defined as follows: [gpio0_ctrl: b0 0x4e] [gpio1_ctrl: b0 0x4f] [gpio2_ctrl: b0 0x50] [gpio3_ctrl: b0 0x51] [ext_clk_ctrl: b0 0x52] [spi/ext_pa_ctrl: b0 0x53] preamble/syncword error tolerance setting *2 start rx_on issue *3 [rf_status: b0 0x0b] n o yes trx_off issue [rf_status: b0 0x0b] read rx data *5 (dio pins) yes next packet to be rx? rxdio_ctrl setting=0b11 [dio_set: b0 0x0c(7-6)] dio_start =0b1 [dio_set:0b 0x0c(0)] n o yes syncword detection (int[13])? [int_source_grp3: b0 0x0f(5)] n o to rf state transition wait flow dclk output? (dclk function pin) n o yes wait *4 *4 wait time should be more than length field + 1 byte data receiving period. 1 byte data is decoded 8 bit data. if using manchester code, 1 byte period becomes 160 s (@ 100kbps). dio pins setting *1 rx completion (int[8]) ? [int_source_grp2: b0 0x0e(0)] fedl7344c/e/j-05 ml7344c/e/j 119/154 (2) fifo mode (less than 64 byte) fifo mode can be selected by rxdio_ctrl[1:0 ]([dio_set: b0 0x0c(7-6)])=0b00. after syncword detection, rx data will be stored into the rx_fifo. upon data rx completion interrupt (int[8] group2) occurs, the host will read rx data from [rd_fifo:b0 0x7f] registers. if crc errors interrupt (int[9] group2) is generated, the next packet can be ready to recei ve without reading all current rx data by setting state_clr1 [state_clr: b0 0x16(1)](rx fifo pointer clear). if fifo-full trigger and fifo-empty trigger are not used, please set 0b0 to both rxfifo_thrh_en([rxfifo_thrh: b0 0x19(7)]) and rxfifo_thrl_en([rxfifo_thrh: b0 0x1a(7)]) . start rx_on issue *1 [rf_status: b0 0x0b] no y es no next packet to be received? y es trx_off issue [rf_status: b0 0x0b] read rx data [rd_fifo:b0 0x7f] tx? y es int[8] clear [int_source_grp2: b0 0x0e] rx fifo trigger level setting [rxfifo_thrh: b0 0x19]=0x00 [rxfifo_thrl: b0 0x1a]=0x00 crc error (int[9])? [int_source_grp2] b0 0x0e(1)] y es rx completion (int[8])? [int_source_grp2] b0 0x0e(0)] no to rf state transition wait flow set tx_on after rx completion? [rf_status_ctrl:b0 0x0a] y es no set trx_off/sleep after rx completion? [rf_status_ctrl:b0 0x0a] y es tx_on issue [rf_status: b0 0x0b] to rf state transition wait flow and tx flow no int[9] clear [int_source_grp2: b0 0x0e] rx fifo pointer clear [state_clr: b0 0x16(1)] *1 at lease following 2 interrupts in the group 2 should be un-masked for data receiving. int[8]: rx completion interrupt int[15]: sync error interrupt fedl7344c/e/j-05 ml7344c/e/j 120/154 (3) fifo mode (65 byte or more) the host must read rx data from the rx_fifo while checking int[5] (group1: fifo-full interrupt) and int[4] (group1: fifo-empty interrupt) in order to avoid fifo-overrun or fifo-underrun. other operations are identical to the fifo mode (less than 64byte). yes n o n o yes fifo-full (int[5]) ? [int_source_grp1: b0 0x0d(5)] int[5] clear [int_source_grp1: b0 0x0d] yes rx fifo-full level disable setting [rx_fifo_thrh: b0 0x19] start read rx data from fifo [ rd fifo:b0 0x7f ] rx completion (int[8])? [int_source_grp2: b0 0x0e(0)] n o int[8] clear [int_source_grp2: b0 0x0e(0)] yes trx_off issue [rf_status: b0 0x0b] tx? n o tx_on issue [rf_status: b0 0x0b] yes set tx_on after rx completion? [rf_status_ctrl:b0 0x0a] yes n o set trx_off/sleep after rx completion? [rf_status_ctrl:b0 0x0a] yes n o to rf state transition wai t flo w to rf state transition wait flow to rf state transition wai t flow and tx flow rx_on issue *1 [rf_status: b0 0x0b] ack_tx? to ack_tx flow n o rx fifo-full level enable setting [rx_fifo_thrh: b0 0x19] rx fifo pointer clear [state_clr: b0 0x16(1)] int[9] clear [int_source_grp2: b0 0x0e(1)] read rx data [rd_fifo:b0 0x7f] next packet to be received ? crc error (int[9])? [int_source_grp2: b0 0x0e(1)] *1 at lease following 2 interrupts in the group 2 should be un-masked for data receiving. int[8]: rx completion interrupt int[15]: sync error interrupt fedl7344c/e/j-05 ml7344c/e/j 121/154 (4) ack transmission ack tx flow is as follows. during rx, ack frame can be set in the tx fifo. yes yes n o write tx data *4 [wr_tx_fifo:b0 0x7c] yes n o n o from rx flow no yes crc error (int[9])? [int_source_grp2] b0 0x0e(1)] tx_on issue *6 [rf_status: b0 0x0b] trx_off issue [rf_status: b0 0x0b] read all rx data [rd_fifo:b0 0x7f] clear tx fifo pointer [state_clr: b0 0x16(0)] *4 ack frame is set to tx fifo. yes n o clear rx fifo pointer [state_clr: b0 0x16(1)] *6 please refer to rf state transition wait flow. start read rx data *3 [rd_fifo:b0 0x7f] yes rx fifo trigger setting *1 [rxfifo_thrh: b0 0x19] [rxfifo_thrl: b0 0x1a] rx_on issue*2 [rf_status: b0 0x0b] no * in case of using interrupt, fifo-full interrupt notification should be on. *3 read address field to check length and packet destination. *2 please refer to rf state transition wait flow. fifo-full interrupt? int[5] [int_source_grp1: b0 0x0d] self addressed? rx completion (int[8])? *5 [int_source_grp2: b0 0x0e(0)] tx completion (int[16])? [int_source_grp3] b0 0x0f(0)] int[8] and [9] clear [int_source_grp2: b0 0x0e] read rx data? end *5 please refer the following ?note? fedl7344c/e/j-05 ml7344c/e/j 122/154 note: if setting ?fast_tx_eb=0b1? or ?auto_tx_en=0b1 or ?rxdone_mode[1:0]=0b01 (move to tx state)? at the [rf_status:ctrl:b0 0x0a] register, moving to tx_on state automatically after rx completion in above flowchart. even if crc error occurs, moving to tx_on state. since crc errors interrupt (int[9] group2) and rx completion interrupt (int[8] group2) occur almost same timeing, therefore in case of crc error interrupt occurs, force_trx_off should be issued by [rf_status:b0 0x0b] register withing the transition time from rx state to tx state(1.188msec), and clear tx fifo pointer by [state_clr:b0 0x16] register. when it is hard to issue force_trx_off during the trasition time due to mcu performance, ?fast_tx?, ?auto_tx? and ?move to tx state after rx completion? should be disabled. (in ?fast_tx?, trnasmitting conditoin depends on [txfifo_thrl:b0 0x18] register.) (5) field check transmission after enabling filedcheck functions, issuing rx_on by [rf_status:b0 0x0b] register. according to the setting of ca_int_ctrl([c_check_ctrl:b0 0x1b(6)]), filed checking result (match or no match) can be notified by the int[14](group2: field checking interrupt ). numbers of unmatched packets can be counted and stored into [addr_chk_ctr_h/l: b1 0x62/0x63]) regist ers. this counter can be cleared by state_clr4 [state_clr: b0 0x16(4)](address check counter clear). start rx_on issue [rf_status] b0 0x0b] field check setting *1 rx flow yes n o read rx data? no field checking compete (int[14])? [int_source_grp2] b0 0x0e(6)] yes int[14] clear [ int source grp2: b0 yes int grp2 clear *2 [int_source_grp2: b0 0x0e] *1 c-field/m-field/a-field check can be possible with the setting below. [c_check_ctrl: b0 0x1b] [m_check_ctrl: b0 0x1c] [a_check_ctrl: b0 0x1d] [c_field_word1-5: b0 0x1e-0x22] [m_field_word1-4: b0 0x21-0x26] [a_field_word1-6: b0 0x27-0x2c] n o yes rx completion (int[8])? [int_source_grp2] b0 0x0e(0)] *2 clear all remaining interrupt in the group 2. fedl7344c/e/j-05 ml7344c/e/j 123/154 (6) cca normal mode after setting cca_en([cca_ctrl: b0 0x39(4)])=0b1, issuing rx_on by [rf_status:b0 0x0b] register. comparing aquired ed average value with cca threshold value in [cca_lvl: b0 0x37] register and noitce the result. after cca execution, cca_e n([cca_ctrl: b0 0x39(4)]) is disabled and rf maintains rx_on state. even if set cca_en=0b1 in the rx_on state, cca execution is possible. n o yes start int[18] clear [int_source_grp3: b0 0x0f(2)] cca_en setting [cca_ctrl: b0 0x39(4)] rx_on issue *1 [rf_status: b0 0x0b] read cca result [cca_ctrl: b0 0x39(1-0)] end trx_off issue [rf_status: b0 0x0b] *1 cca start discontinue cca ? n o yes cca_en setting [cca_ctrl: b0 0x39(4)] cca completion (int[18]) ? [int_source_grp3: b0 0x0f(2)] fedl7344c/e/j-05 ml7344c/e/j 124/154 continuous mode continuous cca mode is executed by issuing rx_on by [rf_statu:b0 0x0b] register after setting cca_en([cca_ctrl: b0 0x39(4)])=0b1 and cca_cpu_en([cca_ctrl: b0 0x39(5)])=0b1. in this mode, cca continues until cca_stop([cca_ctrl: b0 0x39(7)])=0b1 is set. cca completion interupt (int[18]: group3) is not generated. during cca execution, cca_rslt([cca_ctrl: b0 0x39(1-0)]), [cca_prog_l: b0 0x3e], [cca_prog_h: b0 0x3d] are constantly updated. the value will be kept by setting cca_stop([cca_ctrl: b0 0x39(7)])=0b1. *5cca result can be read after cca_stop execution. start rx_on issue *2 [rf_status: b0 0x0b] read cca result *5 cca_rslt[1:0] [cca_ctrl: b0 0x39(1-0)] cca_prog[9:0] [cca_prog_h/l: b0 0x3d/3e] trx_off issue [rf_status: b0 0x0b] cca_en setting cca_cpu_en setting *1 [cca_ctrl: b0 0x39(5-4)] cca_stop setting *6 [cca_ctrl: b0 0x39(7)] *2 cca start *6 cca stop end stop cca ? n o yes ed_done=0b1 ? *4 [ed_ctrl: b0 0x41(4)] yes n o yes n o rx_on completion (int[3]) ? *3 [int_source_grp1: b0 0x0d(3)] *3 rf state transition (rx_on) completion can be confirmed by [rf_status: b0 0x0b]= 0x66. *4 cca result before rx_on are invalid. please read the value after rx_on and ed calculation flag is valid. *1 cca_idle_en should be 0b0 fedl7344c/e/j-05 ml7344c/e/j 125/154 idle detection mode cca is continuously executed untill idle is detected. cca (idle detection mode) will be executing by . issuing rx_on by [rf_statu:b0 0x0b] register after setting cca_en([cca_ctrl: b0 0x39(4)])=0b1, cca_idle_en ([cca_ctrl: b0 0x39(6)])=0b1. start rx_on issue [rf_status: b0 0x0b] n o cca completion (int[18])? [int_source_grp3: b0 0x0f(2)] yes: idle detection int[18] clear [int_source_grp3: b0 0x0f(2)] end cca_idle_en setting *1 cca_en setting [cca_ctrl: b0 0x39(6-4)] *1 cca_cpu_en should be 0b0 fedl7344c/e/j-05 ml7344c/e/j 126/154 (7) high speed carrier checking mode this mode is used for deciding whether continuing rx state or stoping rx state during rx state, based on rssi level and syncword detection time. the value set in the [cca_lvl:b0 0x37] register is used for rssi level decision, continuous operation timer is used for syncword detection time decision. after decision, operation will automaticall switch to ? either sleep state or rx state. start fast_det_mode_en setting cca_en setting [cca_ctrl:b0 0x39(4-3)] carrier detected? (automatic) keep rx state yes: busy detection n o: idle detection syncword detection? receive rx data yes n o *2 sleep command (automatic) sleep state end cca threshold setting [cca_lvl:b0 0x37] continuous operation timer setting [wut_clk_set:b0 0x2e] [wut_duration:b0 0x31] rx_on issue *1 [rf_status: b0 0x0b] *1 cca start *2: expiring the continuous operation timer fedl7344c/e/j-05 ml7344c/e/j 127/154 (8) ed scan ed value will be automatically acquired by issuing rx_on by [rf_statu:b0 0x0b] register after setting ed_calc_en ([ed_ctrl: b0 0x41(7)])=0b1. ed value is constanty updated when ed_rslt_set ([ed_ctrl:b0 0x41(3)] )=0b0. start n o ed value calculation completion? [ed_ctrl:b0 0x41(4)] yes ed calculations enable setting ed value constantly updated setting [ed_ctrl: b0 0x41(7,3)] read ed value [ed_rslt:b0 0x3a] yes channel change ? n o rf channel change [ch_set:b0 0x09] trx_off issue [rf_status:b0 0x0b] rx_on issue [rf_status:b0 0x0b] these processes are not necessary if 250 swai t is added after rf channel change setting. general purpose timer start [gt_se t :b0 0x32] n o yes to rf state transition wait flow (*1) (*1) general purpose timer setting example if 250 s wait is programmed using general purpose timer 1, the following registers can be used. [gt_clk_set:b0 0x33] 0x01(128 division) [gt_interval1:b0 0x34] 0x04(timer setting) [gt_set:b0 0x32] 0x03(2mhz clock, timer start) ed value will be acquired by enabling ed calculation after rx_on issue, ed value will be constantly updated constantly general timer int ? [int_source_grp3:b0 0x0f] int[22]/int[23] general timer int clear [int_source_grp3:b0 0x0f] int[22]/int[23] fedl7344c/e/j-05 ml7344c/e/j 128/154 sleep sequence (1) sleep sleep can be executed by setting sleep_en([sleep/wu_set:b0 0x2d(0)])=0b1. sleep can be released by setting sleep_en=0b0. if vco calibration automatic execution setting auto_vcocal_en ([vco_cal_start:b0 0x6f (4)])=0b1, vco calibration is performed after clock stabilization completion interrupt (int[0] group1) from sleep release. start sleep state [sleep/wu_set:b0 0x2d] yes end sleep released? n o yes clock stabilization completion(int[0])? [int_source_grp1:b0 0x0d(0)] n o sleep released [sleep/wu_set: b0 0x2d] automatic vco calibration? [vco_cal_start:b0 0x6f(4)] n o yes vco calibration completion (int[1])? [int_source_grp1:b0 0x0d(1)] n o yes fedl7344c/e/j-05 ml7344c/e/j 129/154 (2) wake-up timer by setting the following registers, after sleep, automatically wake-up to rx_on state. if syncword is detected before continuous operation ti mer-up, rx_on will be continued to receive a packet. after receiving rx completion interrupt(int[8]: group2), by reading int group2, mcu can determine read rx data or not. in order to re-enter sleep state, executing sleep command after clearing all interrupts in int group2. if generating sync error interrupt(int[15]: group2), executing sleep command after clearing rx_fifo and int group2. if syncword cannot be detected, automatically go back to sleep state after continuous operation timer-up. [wake-up timer setting] wakeup_en([sleep_set:b0 0x2d(4)]) =0b1 rx_duration_en([sleep_set:b0 0x2d(5)])=0b1 wakeup_mode([ sleep_set:b0 0x2d(6)])=0b0 [wut_clk_set:b0 0x2e] [wut_interval_h:b0 0x2f] [wut_interval_l:b0 0x30] [rx_duration:b0 0x31] [field check function setting] [c_check_ctr:b0 0x1b] [m_check_ctrl:b0 0x1c] [a_check_ctrl:b0 0x1d] [c_field_word1:b0 0x1e] to [c_field_word5:b0 0x22] [m_field_word1:b0 0x23] to [m_field_word4:b0 0x26] [a_field_word1:b0 0x27] to [a_field_word6:b0 0x2c] *1 at lease following 2 interrupts in the group 2 should be un-masked for data receiving. int[8]: rx completion interrupt int[15]: sync error interrupt start *1 sleep execution [sleep/wu_set:b0 0x2d(0)] rx completion(int[8])? [int_source_grp2:b0 0x0e(0)] sync error (int[15])? [int_source_grp2:b0 0x0e(7)] yes n o n o yes read int_source_grp2 [int_source_grp2:b0 0x0e] field checking (int[14])? [int_source_grp2:b0 0x0e(6)] yes n o read all rx data from rx_fifo [rd_fifo:b0 0x7f] clear int_source_grp2 [int_source_grp2:b0 0x0e] rx fifo clear [sate_clr:b0 0x16(1)] sleep execution [sleep/wu_set:b0 0x2d(0)] wake-up timer off)? n o wake-up timer off execution [sleep/wu_set:b0 0x2d(4)] end fedl7344c/e/j-05 ml7344c/e/j 130/154 error process (1) sync error when out-of-sync is detected during data reception af ter syncword detection, sync error interrupt (int[15] group2) will be generated, rx completion interrupt (int[8]: group2) will not be generated. if sync error interrupt occurs, issuing state_clr1 [state_clr: b0 0x16(1)](rx fifo pointer clear) without read rx_fifo data and clear sync error interrupt. ?data reception? indicates receiving data (l-fie ld, data, crc). after syncword detection. start rx_on issue *1 [rf_status:b0 0x0b] yes n o next packet received? yes clear rx fifo [state_clr:b0 0x16(1)] int[15] clear [int_source_grp2:b0 0x0e] n o out-of-sync detection normal reception (to rx flow) trx_off issue [rf_status:b0 0x0b] rf state transition wait flow sync word error (int[15])? [int_source_grp2:b0 0x0d(7)] *1 at lease following 2 interrupts in the group 2 should be un-masked for data receiving. int[8]: rx completion interrupt int[15]: sync error interrupt fedl7344c/e/j-05 ml7344c/e/j 131/154 (2) tx fifo access error if one of the following conditions is met, tx fifo access error interrupt (int[20]: group3) will be generated. after tx data request accept completion interrupt (int[17]: group3] was generated, next packet is written to the tx_fifo without transmiting the current tx data. data write overflow occurs to the tx_fifo. no tx data in the tx_fifo during tx data transimission. when tx fifo acccess error interrupt occurs, issuing trx_off after tx completion interrupt (int[16]: group3) is recognized, or issueing force_trx_off by [rf_status:b0 0x0a] register without waiting for tx completion interrupt. after that, issuing tx fifo point er clear by [state_clr:b0 0x16] register and clear remaining interrupts relative with tx in the [int_source_grp3:b0 0x0f] register. if tx fifo access error occurs, subquent tx data will be inverted. crc error should be detected at rexeiver side even if trx_off is issued when tx completion interrupt detected. start fast_tx setting [rf_status_ctrl:b0 0x0a] [txfifo_thrh/l:b0 0x17/18] n o yes n o next packet tx ? yes trx_off issue [rf_status:b0 0x0b] tx fifo access error (int[20])? [nt_source_grp3:b0 0x0f(4)] normal tx (to tx flowchart) n o yes yes tx completion (int[16]) ? [int_source_grp3:b0 0x0f(0)] n o forced to stop tx ? force_trx_off issue [rf_status:b0 0x0b] tx fifo pointer clear [state_clr:b0 0x16(0)] clear int grp3 int[16]-[20] [int s ource grp3 : b0 0x0f] rf state transition wait flow write tx data *1 [wr_tx_fifo:b0 0x7c] *1 if data written to fifo exceed thfifo_thrl[5:0] [txfifo_thrl:b0 0x18(5-0)]+1, tx will start. (length is included in the data length written to fifo) fedl7344c/e/j-05 ml7344c/e/j 132/154 (3) rx fifo access error if one of the following conditions is met, rx fifo access error interrupt (int[12]: group2) will be generated. rx data overflow occurs to rx_fifo read rx_fifo during no data in the rx_fifo when rx fifo acccess error interrupt occurs, issuing trx_off after rx completion interrupt (int[8]: group2) is recognized, or issueing force_trx_off by [rf_status:b0 0x0b] register without waiting for rx completion interrupt. after that, issuing rx fifo pointer clear by [state_clr:b0 0x16] register and clear remaining interrupts in the [in t_source_grp2:b0 0x0e] register. start n o yes n o next packet to be received? yes trx_off issue [rf_status:b0 0x0b] rx fifo access error (int[12])? [nt_source_grp2:b0 0x0e(4)] normal rx (to rx flowchart) n o yes yes rx completion (int[8]) ? [int_source_grp2:b0 0x0e(0)] n o forced to stop rx ? force_trx_off issue [rf_status:b0 0x0b] rx fifo pointer clear [state_clr:b0 0x16(1)] clear int grp2 [int _ source _ grp2:b0 0x0e] rf state transition wait flow rx_on issue [rf_status:b0 0x0b] fedl7344c/e/j-05 ml7344c/e/j 133/154 (4) pll unlock detection tx during tx, if pll unlock is detected, pll unlock interrupt (int[2] group1) will be generated. when pll unlock interrupt occurs, force_trx_ off is automaticcally issued and move to idle state. set_trx[3:0] ([rf_status: b0 0x0b(3-0)]) will be written to 0b00 11(force_trx_off). pll unlock might be occurred when vco calibration value is not correct. please confirm vco calibration or perform vcocalibration again. after pll unlock interrupt occurs, max. 147 s is necessary to move to idle state. please wait for at least 147 s before next tx, rx or vco calibration is performed. n o next packet tx? yes pll unlock (int[12])? [int_source_grp1:b0 0x0d(2)] normal tx (to tx flowchart) n o yes end int[12] clear [int_source_grp1:b0 0x0d(2)] tx_on issue [rf_status:b0 0x0b] wait trx_off(idle) (147 sec) write tx data [wr_tx_fifo:b0 0x7c] * force_trx_off is issued automatically . start fedl7344c/e/j-05 ml7344c/e/j 134/154 rx during rx, if pll unlock is detected, pll unlock interrupt (int[2] group1) will be generated. during rx, even if pll unlock is detected, rx state is maintained (do not move to idle state). please receive next packet after clearing pll unlock interrupt. when pll unlock interrupt occurs frequently, pll unlock cause mitgh be due to the mismatch of the vco circuit and using frequency band. please use after removing the cause by circuit verification. start n o next packet to be received? yes pll unlock (int[2])? [int_source_grp1:b0 0x0d (2)] normal rx (to rx flowchart) n o yes end int[2] clear [int_source_grp1:b0 0x0d(2)] rx_on issue [rf_status:b0 0x0b] force_trx_off issue [rf_status:b0 0x0b] fedl7344c/e/j-05 ml7344c/e/j 135/154 data rate change sequence when changing data rate during operation, registers relative data rate should be set in trx_off state and issuing rst1([rst_set: b0 0x01(1)])(modem reset) after register setting. if not issuing rst1, ml7344 can not transmit or receive correctlly. *1 tx_on or rx_on state *2 relating registers refer to ?data rate setting function? trx_off issue [rf_status:b0 0x0b] change data rate *2 start *1 rst1 issue [rst_set:b0 0x0b] end fedl7344c/e/j-05 ml7344c/e/j 136/154 timing chart the followings are operation timing for major functions. note: bold characters indicate pins related signals . non bold characters indicate internal signals. start-up *1 : for wake-up timing of vdd and resetn, please refer to the ?reset characteristics?. *2 : when setting xtal_en(clk_set2:b0 0x03(4)))=0b1, it is possible to adjust to 10/50/250/500 s, by setting osc_w_sel[1:0]([adc_clk_set: b1 0x08(6-5)]). when using tcxo (tcxo_en([clk_set2:b0 0x03( 6)])=0b1), clock stabilization time is 5.5 s. *3 : [vco_cal_start:b0 0x6f] and [rf_status:b0 0x 0b] resister access is possible, but process is pending until reg_wait_done is asserted. 50 s *2 resetn osc/reg enable vdd 500 s *1 clock stabilization time regulator voltage wake up time reg_wait_done spi access :w prohibited rf operation possible int[0] (clk stabilized completion) [int_source_grp1: b0 0x0d] bank0, 1 & 3 access possible all bank&fifo access possible regulator stabilization time 625 s *3 fedl7344c/e/j-05 ml7344c/e/j 137/154 tx *1 : when txdone_mode[1:0]([rf_status_ctrl: b0 0x0a(1-0)]) = 0b00(default), set_trx[3:0] ([rf_status: b0 0x0b(3-0)]) will be set to 0x8(trx_off) automatically, upon detection of tx completion. *2 : data tx time calculation is as follows: data tx time [sec] = (number of tx bits+3)1bit tx duration time[sec] 1bit tx duration time [sec] = 1/data rate [bps] *3 : when setting txdio_ctrl[1:0]([dio_set: b0 0x0c(5-4)])=0b01. 0x8 ( trx_off) a ir scen fifo write tx_on command int[17] (tx data request accept completion) [int_source_grp3: b0 0x0f] 0x8 ( trx_off) set_trx[3:0] [rf_status: b0 0x0b] get_trx[3:0] [rf_status: b0 0x0b] int[3] (rf state transition completion) [int_source_grp1: b0 0x0d] int[16] (tx completion) [int_source_grp3: b0 0x0f] 1406 s pa_on 1271 s dclk output (*3) 0x9 ( tx_on) tx completion interrupt *1 data tx time *2 int[3] clear command 0x9 ( tx_on) 0x8 ( trx_off) 0x8 ( trx_off) 147 s 143 s 0.4 bit time ( a t 1 00 kb ps , 4 s ) tx_on 1222 s 144 s fedl7344c/e/j-05 ml7344c/e/j 138/154 rx *1 : when setting rxdio_ctrl[1:0]([dio_set: b0 0x0c(7-6)])=0b10 or 0b11. 0x8 ( trx_off) 0x6 ( rx_on) scen rx_on int[3]clear command 0x6 ( rx_on) 0x8 ( trx_off) 0x8 ( trx_off) 0x8 ( trx_off) set_trx[3:0] [rf_status: b0 0x0b] get_trx[3:0] [rf_status: b0 0x0b] 471 s 4 s trx_off command int[3] (rf state transition completion ) [int_source_grp1: b0 0x0d] int[8] (rx completion) [int_source_grp2: b0 0x0e] demod data pb sync word length data crc int[13] (syncword detection) [int_source_grp2: b0 0x0e] dclk output (*1) 1 to 2 bit time ( at 100kb p s , 10 to 20 s ) dio data output command (when dio function is used) rx enable fedl7344c/e/j-05 ml7344c/e/j 139/154 transition from tx to rx transition from rx to tx set_trx[3:0] [rf_statu: b0 0x0b] get_trx[3:0] [rf_status: b0 0x0b] int[3] (rf state transition completion) [int_source_grp1: b0 0x0d] pa_on 0x9(tx_on) 0x6(rx_on) 0x6(rx_on) 0x9(tx_on) 611 s 143 s 0x6(rx_on) 0x9(tx_on) 0x9(tx_on) 0x6(rx_on) set_trx[3:0] [rf_status: b0 0x0b] get_trx[3:0] [rf_status: b0 0x0b] 1188 s int[3] (rf state transition completion) [int_source_grp1: b0 0x0d] pa_on 1053 s fedl7344c/e/j-05 ml7344c/e/j 140/154 transition from idle to sleep *1 : clock input should be required for sleep transition. if tcxo is stopped during sleep stae, please wait 0.3 s after sleep command issued ( sleep_en([sleep/wu_set: b0 0x2d(0)])=0b1 ) and then stop tcxo. transition from tx/rx to sleep *1 : if tcxo is used, please stop tcxo(clock) input after 1.3 s from int[3] notification. by setting sleep command (sleep_en ([sleep/wu_set: b0 0x2d(0)])=0b1). osc/reg enable clk_init_done [clk_set : b0 0x02] sleep command 0.3 s sleep transition time *1 sleep_en [sleepwu_set: b0 0x2d] 0x3(force_trx_off) 0x8(trx_off) 0x8(trx _ off) set_trx[3:0] [rf_status: b0 0x0b] get_trx[3:0] [rf_status: b0 0x0b] by sleep_en=0b1, automatic switching osc/reg enable 1.3 s time required from int[3] to sleep *1 sleep_en [sleepwu_set: b0 0x2d] set_trx[3:0] [rf_status: b0 0x0b] get_trx[3:0] [rf_status: b0 0x0b] int[3] (rf state transition completion) [int_source_grp1: b0 0x0d] 1 s clk_init_done [clk_set: b0 0x02] 0x6(rx_on) 0x9(tx_on) 0x3(force_trx_off) by sleep_en=0b1, automatic switching 0x6(rx_on) 0x9(tx_on) 0x8(trx_off) from rx_on:4 s from tx_on:147 s sleep command fedl7344c/e/j-05 ml7344c/e/j 141/154 transition from sleep to idle *1: when setting xtal_en([clk_set2: b0 0x03(4)])=0b1, it is possible to adjust to 10/50/250/500 s , by setting [adc_clk_set: b1 0x08(6-5)]. is oscillation cuircuits start-up time, and max. is 500 s. when using tcxo (tcxo_en([clk_set2:b0 0x03(6)])=0b1), clock stabilization time is 5 s. *2: [vco_cal_start:b0 0x6f] and [set_trx:b0 0x0b] registers access is possible, but process is pending until reg_wait_done is asserted. 50 s + *1 osc/reg enable clock stabilization time reg_wait_done 1125 s *2 rfoperation possible int[0] (clk stabilized complete) [int_source_grp1: b0 0x0d] sleep_en [sleepwu_set: b0 0x2d] sleep_en=0b0 setting regulator stabilization time sleep mode1: register access possible sleep mode2: register & fifo access possible resisters and fifos access possible fedl7344c/e/j-05 ml7344c/e/j 142/154 high speed carrier checking mode *1: clock input should be required for sleep transition. if tcxo is stopped during sleep state, please wait 1.3 s from int[3] and then stop tcxo. 0x8(trx_off) 0x6(rx_on) scen rx_on command int[3] clear command 0x6(rx_on) 0x8(trx_off) 0x8(trx_off) 0x8(trx_off) set_trx[3:0] [rf_status: b0 0x0b] get_trx[3:0] [rf_status: b0 0x0b] int[3] (rf state transition completion) [int_source_grp1: b0 0x0d] 471 s 4 s cca on-going flag sleep flag 1.3 s (*1) 1 s 166.5 s condition) use tcxo ed averaging: 1 time fedl7344c/e/j-05 ml7344c/e/j 143/154 registers register map it is consist of 4 banks, bank0, bank1, bank2 and bank3. each bank has address space of 0x00 to 0x7f, 128 byte in total. the space shown as gray highlighted part is not implemented in lsi or reserved bits. reserved bits may be assigned closed function. please use default values to reserv ed bits, when write a register which contains reserved bits. regarding reserved register, access is inhibited. bank3 is closed bank, then access is limited.. transition between banks can be controlled by bit 3-0 ( bank[3:0] ) of [bank_sel] register. : implemented as functionable register : impelemted as reserved bits bank0 bit address symbol (# test register) 7 6 5 4 3 2 1 0 description 0x00 bank_sel register access bank selection 0x01 rst_set software reset setting 0x02 clk_set1 clock configuration 1 0x03 clk_set2 clock configuration 2 0x04 pkt_ctrl1 packet configuration 1 0x05 pkt_ctrl2 packet configuration 2 0x06 drate_set data rate setting 0x07 data_set1 tx/rx data configuration 1 0x08 data_set2 tx/rx data configuration 2 0x09 ch_set rf channel setting 0x0a rf_status_ctrl rf auto status transition control 0x0b rf_status rf state setting and status indication 0x0c dio_set dio mode configuration 0x0d int_source_grp1 interrupt status for int0 to int7 0x0e int_source_grp2 interrupt status for int8 to int15 (rx) 0x0f int_source_grp3 interrupt status for int16 to int23 (tx) 0x10 int_en_grp1 interrupt mask for int0 to int7 0x11 int_en_grp2 interrupt mask for int8 to int15 0x12 int_en_grp3 interrupt mask for int16 to int23 0x13 crc_err_h crc error status (high byte) 0x14 crc_err_m crc error status (middle byte) 0x15 crc_err_l crc error status (low byte) 0x16 state_clr state clear control 0x17 txfifo_thrh tx fifo-full level setting 0x18 txfifo_thrl tx fifo-empty level setting and tx trigger level setting in fast_tx mode 0x19 rxfifo_thrh rx fifo-full level setting 0x1a rxfifo_thrl rx fifo-empty level setting 0x1b c_check_ctrl control field (c-field) detection setting 0x1c m_check_ctrl manufacture id field (m-field) detection setting 0x1d a_check_ctrl address field (a-field) detection setting 0x1e c_field_code1 c-field setting code #1 0x1f c_field_code2 c-field setting code #2 fedl7344c/e/j-05 ml7344c/e/j 144/154 bank0 (continued) bit address symbol (# test register) 7 6 5 4 3 2 1 0 description 0x20 c_field_code3 c-field setting code #3 0x21 c_field_code4 c-field setting code #4 0x22 c_field_code5 c-field setting code #5 0x23 m_field_code1 m-field 1 st byte setting code #1 0x24 m_field_code2 m-field 1 st byte setting code #2 0x25 m_field_code3 m-field 2 nd byte setting code #1 0x26 m_field_code4 m-field 2 nd byte setting code #2 0x27 a_field_code1 a-field 1 st byte setting 0x28 a_field_code2 a-field 2 nd byte setting 0x29 a_field_code3 a-field 3 rd byte setting 0x2a a_field_code4 a-field 4 th byte setting 0x2b a_field_code5 a-field 5 th byte setting 0x2c a_field_code6 a-field 6 th byte setting 0x2d sleep/wu_set sleep execution and wake-up operation setting 0x2e wut_clk_set wake-up timer clock division setting 0x2f wut_interval_h wake-up timer interval setting (high byte) 0x30 wut_interval_l wake-up timer interval setting (low byte) 0x31 wu_duration continue operation timer (after wake-up) setting 0x32 gt_set general purpose timer configuration 0x33 gt_clk_set general purpose timer clock division setting 0x34 gt1_timer general purpose timer #1 setting 0x35 gt2_timer general purpose timer #2 setting 0x36 cca_ignore_lvl ed threshold level setting for excluding cca judgement 0x37 cca_lvl cca threshold level setting 0x38 cca_abort timing setting for forced termination of cca operation 0x39 cca_ctrl cca control setting and result indication 0x3a ed_rslt ed value indication 0x3b idle_wait_h idle detection period setting during cca (high 2bits) 0x3c idle_wait_l idle detection period setting during cca (low byte) 0x3d cca_prog_h idle judgement elapsed time indication during cca (high 2 bits) 0x3e cca_prog_l dle judgement elapsed time indication during cca (low byte) 0x3f reserved reserved 0x40 vco_vtrslt vco voltage adjustment result indication 0x41 ed_ctrl ed detection control setting 0x42 txpr_len_h tx preamble length setting (high byte) 0x43 txpr_len_l tx preamble length setting (low byte) 0x44 postamble_set postamble length and pattern setting 0x45 sync_condition1 rx preamble setting and ed threshold check setting 0x46 sync_condition2 ed threshold setting during synchronization 0x47 sync_condition3 bit error tolerance setting in rx preamble and syncword detection 0x48-4c reserved reserved 0x4d mon_ctrl monitor function setting 0x4e gpio0_ctrl gpio0 pin (pin #16) configuration setting 0x4f gpio1_ctrl gpio1 pin (pin #17) configuration setting fedl7344c/e/j-05 ml7344c/e/j 145/154 bank0 (continued) bit address symbol (# test register) 7 6 5 4 3 2 1 0 description 0x50 gpio2_ctrl gpio2 pin (pin #18) configuration setting 0x51 gpio3_ctrl gpio3 pin (pin #19) configuration setting 0x52 extclk_ctrl ext_clk pin (pin #10) configuration setting 0x53 spi/ex_pa_ctrl spi interface io configuration/external pa control setting 0x54 if_freq_h if frequency setting (high byte) 0x55 if_freq_l if frequency setting (low byte) 0x56-61 reserved reserved 0x62 osc_adj1 coarse adjustment of load capacitance for oscillation circuit 0x63 osc_adj2 fine adjustment of load capacitance for oscillation circuit 0x64-65 reserved reserved 0x66 rssi_adj rssi value adjustment 0x67 pa_mode pa mode setting / pa regulator coarse adjustment 0x68 pa_reg_fine_adj pa regulator fine adjustment 0x69 pa_adj pa gain adjustment 0x6a-6d reserved reserved 0x6e vco_cal vco calibration setting or status indication 0x6f vco_cal_start vco calibration execution 0x70 clk_cal_set low speed clock calibration control 0x71 clk_cal_time low speed clock calibration time setting 0x72 clk_cal_h low speed clock calibration result indication (high byte) 0x73 clk_cal_l low speed clock calibration result indication (low byte) 0x74 reserved 0x75 sleep_int_clr interruption clear setting during sleep state 0x76 rf_test_mode tx test pattern setting 0x77 stm_state state machine status / synchronization status indication 0x78 fifo_set fifo readout setting 0x79 rx_fifo_last rx fifo data usage status indication 0x7a tx_pkt_len_h tx packet length setting (high byte) 0x7b tx_pkt_len_l tx packet length setting (low byte) 0x7c wr_tx_fifo tx_fifo 0x7d rx_pkt_len_h rx packet length indication (high byte) 0x7e rx_pkt_len_l rx packet length indication (low byte) 0x7f rd_fifo fifo read fedl7344c/e/j-05 ml7344c/e/j 146/154 bank1 bit address symbol (# test register) 7 6 5 4 3 2 1 0 description 0x00 bank_sel register access bank select 0x01 clk_out clk_out (gpion) output frequency setting 0x02 tx_rate_h tx data rate conversion setting (high 4 bits) 0x03 tx_rate_l tx data rate conversion setting (low byte) 0x04 rx_rate1_h rx data rate conversion setting 1 (high 4 bits) 0x05 rx_rate1_l rx data rate conversion setting 1 (low byte) 0x06 rx_rate2 rx data rate conversion setting 2 0x07 reserved reserved 0x08 adc_clk_set rssi adc clock frequency setting 0x09-0a reserved reserved 0x0b pll_lock_detect pll lock detection setting 0x0c-0x12 reserved reserved 0x13 rssi_mag_adj scale factor setting for ed value conversion 0x14 rssi_val rssi value indication 0x15 afc_ctrl afc control setting 0x16 crc_poly3 crc polynomial setting 3 0x17 crc_poly2 crc polynomial setting 2 0x18 crc_poly1 crc polynomial setting 1 0x19 crc_poly0 crc polynomial setting 0 0x1a pll_div_set pll frequency division setting 0x1b txfreq_i tx frequency setting (i counter) 0x1c txfreq_fh tx frequency setting (f counter high 4 bits) 0x1d txfreq_fm tx frequency setting (f counter middle byte) 0x1e txfreq_fl tx frequency setting (f counter low byte) 0x1f rxfreq_i rx frequency setting (i counter) 0x20 rxfreq_fh rx frequency setting (f counter high 4 bits) 0x21 rxfreq_fm rx frequency setting (f counter middle byte) 0x22 rxfreq_fl rx frequency setting (f counter low byte) 0x23 ch_space_h channel space setting (high byte) 0x24 ch_space_l channel space setting (low byte) 0x25 sync_word_len syncword length setting 0x26 sync_word_en syncword enable setting 0x27 sync_word1_set0 syncword #1 setting (bit24 to 31) 0x28 sync_word1_set1 syncword #1 setting (bit16 to 23) 0x29 sync_word1_set2 syncword #1 setting (bit8 to 15) 0x2a sync_word1_set3 syncword #1 setting (bit0 to 7) 0x2b sync_word2_set0 syncword #2 setting (bit24 to 31) 0x2c sync_word2_set1 syncword #2 setting (bit16 to 23) 0x2d sync_word2_set2 syncword #2 setting (bit8 to 15) 0x2e sync_word2_set3 syncword #2 setting (bit0 to 7) 0x2f fsk_ctrl gfsk/fsk modulation timing resolution setting fedl7344c/e/j-05 ml7344c/e/j 147/154 bank1 (continued) bit address symbol (# test register) 7 6 5 4 3 2 1 0 description 0x30 gfsk_dev_h gfsk frequency deviation setting (high 6 bits) 0x31 gfsk_dev_l gfsk frequency deviation setting (low byte) 0x32 fsk_dev0_h/gfil0 fsj 1 st frequency deviation setting (high 6 bits) / gaussian filter coefficient setting 0 0x33 fsk_dev0_l/gfil1 fsj 1 st frequency deviation setting (low byte) / gaussian filter coefficient setting 1 0x34 fsk_dev1_h/gfil2 fsj 2 nd frequency deviation setting (high 6 bits) / gaussian filter coefficient setting 2 0x35 fsk_dev1_l/gfil3 fsj 2 nd frequency deviation setting (low byte) / gaussian filter coefficient setting 3 0x36 fsk_dev2_h/gfil4 fsj 3 rd frequency deviation setting (high 6 bits) / gaussian filter coefficient setting 4 0x37 fsk_dev2_l/gfil5 fsj 3 rd frequency deviation setting (low byte) / gaussian filter coefficient setting 5 0x38 fsk_dev3_h/gfil6 fsj 4 th frequency deviation setting (high 6 bits) / gaussian filter coefficient setting 6 0x39 fsk_dev3_l fsj 4 th frequency deviation setting (low byte) 0x3a fsk_dev4_h fsj 5 th frequency deviation setting (high 6 bits) 0x3b fsk_dev4_l fsj 5 th frequency deviation setting (low byte) 0x3c fsk_tim_adj4 fsk 4 th frequency deviation hold timing setting 0x3d fsk_tim_adj3 fsk 3 rd frequency deviation hold timing setting 0x3e fsk_tim_adj2 fsk 2 nd frequency deviation hold timing setting 0x3f fsk_tim_adj1 fsk 1 st frequency deviation hold timing setting 0x40 fsk_tim_adj0 fsk no-deviation frequency (carrier frequency) hold timing setting 0x41-4c reserved reserved 0x4d vco_cal_min_i vco calibration low limit frequency setting (i counter) 0x4e vco_cal_min_fh vco calibration low limit frequency setting (f counter high 4 bits) 0x4f vco_cal_min_fm vco calibration low limit frequency setting (f counter middle byte) fedl7344c/e/j-05 ml7344c/e/j 148/154 bank1 (continued) bit address symbol (# test register) 7 6 5 4 3 2 1 0 description 0x50 vco_cal_min_fl vco calibration low limit frequency setting (f counter low byte) 0x51 vco_cal_max_n vco calibration upper limit frequency setting 0x52 txvcal_min tx vco calibration low limit value indication and setting 0x53 txvcal_max tx vco calibration upper limit value indication and setting 0x54 rxvcal_min rx vco calibration low limit value indication and setting 0x55 rxvcal_max rx vco calibration upper limit value indication and setting 0x56 demod_set0 demodulator configuration #0 0x57 demod_set1 demodulator configuration #1 0x58 demod_set2 demodulator configuration #2 0x59 demod_set3 demodulator configuration #3 0x5a demod_set4 demodulator configuration #4 0x5b demod_set5 demodulator configuration #5 0x5c demod_set6 demodulator configuration #6 0x5d demod_set7 demodulator configuration #7 0x5e demod_set8 demodulator configuration #8 0x5f demod_set9 demodulator configuration #9 0x60 demod_set10 demodulator configuration #10 0x61 reserved 0x62 addr_chk_ctr_h address check counter indication (high 3 bits) 0x63 addr_chk_ctr_l address check counter indication (low byte) 0x64 wht_init_h whitening initialized state setting (high 1 bit) 0x65 wht_init_l whitening initialized state setting (low byte) 0x66 wht_cfg whitening polynomial setting 0x67-7e reserved reserved 0x7f id_code id code bank2 bit address symbol (# test register) 7 6 5 4 3 2 1 0 description 0x00 bank_sel register access bank select 0x01-2b reserved closed register 0x2c lo_bias_ip local bias adjustment (i-phase positive) 0x2d lo_bias_in local bias adjustment (i-phase negative) 0x2e lo_bias_qp local bias adjustment (q-phase positive) 0x2f lo_bias_qn local bias adjustment (q-phase negative) 0x30-7f reserved closed register fedl7344c/e/j-05 ml7344c/e/j 149/154 application circuit example the below diagram does not show decoupling capacitors for lsi power pins. 10uf decoupling capacitor should be pl aced to common 3.3v power pins . murata lqw15series inductors are recommended. fedl7344c/e/j-05 ml7344c/e/j 150/154 package dimensions remarks for surface mount type package surface mount type package is very sensitive affected by heating from reflow process, humidity during storaging therefore, in case of reflow mouting process, please contact sales representative about product name, package name, number of pin, package code and required reflow process condition (reflow method, temperature, number of reflow process), storage condition. fedl7344c/e/j-05 ml7344c/e/j 151/154 footprint pattern (recommendation) when laying out pc boards, it is important to design the foot pattern so as to give consideration to ease of mounting, bonding, positioning of parts, reliability, wiring, and elimination of slder bridges. the optimum design for the foot pattern varies with the materials of the substrate, the sort and thichness of used soldering paste, and the way of soldering. therefore when laying out the foot pattern on the pc boards, refer to this figure which mean the mounting area that the packag e leads are allowable for soldering pc boards. p-wqfn32-0505-0.50-a63 fedl7344c/e/j-05 ml7344c/e/j 152/154 revision history page document no. date previous edition current edition description fedl7344c/e/j-01 july 8, 2013 ? ? initial release 3 3 correct mistype(100mw tx power consumption) 13 13 add rx power consumption of ml7344xc. fedl7344c/e/j-02 july 9, 2013 21 21 change figure in dio interface characteristics. initial level of dclk is modified from l to h. 15 15 added min. / max. value for tx power 17 17 added max. value for minimum rx sensitivity. 58 58 corrected formula of wake-up timer interval and continuous operation timer. 81, 96 81, 96 updated a formula for calculating the ed value. 89, 90 added typical values for pa adjustments. 98 98 removed ?bpf adjustment?. this is no longer necessary. 99 98 added ? rx mode setting.? 132 134 added tx_on signal in ?tx timing-chart? 148 150 added note of len_lf_en[pkt_ctrl1: b0 0x04(5)] and pkt_format[pkt_ctrl1: b0 0x04(1-0)]. 176 178 corrected formula of wake-up timer interval in function description. 176 178 corrected formula of continuous operation timer interval in function description. 193 195 corrected function description of ext_clk pin configuration setting (extclk_io_cfg [extclk _ ctrl: b0 0x52 ( 2-0 ) ] ) 194 196 corrected function description of external setting ext_pa_cnt[spi/ext_pa_ctrl: b0 0x53(1)] and ext_pa_en[spi/ext_pa_ctrl: b0 0x53(0)] 204 207 added note of len_lf_en[pkt_ctrl1: b0 0x04(5)] and pkt_format[pkt_ctrl1: b0 0x04(1-0)]. 208 211 added note of clk_out function fedl7344c/e/j-03 apr 15, 2014 144, 239 143, 238 removed a register [bpf_adj: b2 0x10]. bpf adjustment is no longer necessary. fedl7344c/e/j-05 ml7344c/e/j 153/154 page document no. date previous edition current edition description - - removed spxo support 12 12 removed master clock accuracy(acmck2) 14 14 corrected regulator voltage output when sleep mode(sub_reg) 15 15 corrected typ. value of tx power. 18 18 corrected typ. value of blocking (470mhz band). 70 70 corrected compensation range of afc 198 - removed a register [iff_adj_h: b0 0x5e] 198 - removed a register [iff_adj_l: b0 0x5f] fedl7344c/e/j-04 oct 2, 2014 216 215 removed registers bit6-4 of [afc_ctrl: b1 0x15] 9 9 added description of ext_clk pin 88 88 changed frequency from 32.768khz to 44khz in the example. - 89-90 added antenna switching function. 97 97 modified registers 135 138 corrected tx-rx transition time in timing chart 136 139 corrected rx start-up time in timing chart 139 142 corrected rx start-up time and cca time in timing chart 176 179 added note of rcosc_mode[sleep/wu_set: b0 0x2d(3)] 177 180 added note of wudt_clk_set[wut_clk_set: b0 0x2e(7-4)] - 195 added [2div_ctrl: b0 0x48] and [ant_ctrl: b0 0x4c] fedl7344c/e/j-05 jan 20, 2015 234 238 added equation for setting value and note of [demod_set6: b1 0x5c] fedl7344c/e/j-05 ml7344c/e/j 154/154 notes no copying or reproduction of this document, in part or in whole, is permitted without the consent of lapis semiconductor co., ltd. the content specified herein is subject to change for improvement without notice. examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the information specified in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, lapis semiconductor shall bear no responsibility for such damage. the technical information specified herein is intended only to show the typical functions of and examples of application circuits for the products. lapis semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by lapis semiconductor and other parties. lapis semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. the products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). the products specified in this document are not designed to be radiation tolerant. while lapis semiconductor always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any product, such as derating, redundancy, fire control and fail-safe designs. lapis semi conductor shall bear no responsibility whatsoever for your use of any product outside of the prescribed sc ope or not in accordance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical inst rument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). lapis semiconductor shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for any such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specified herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law. copyright 2013-2015 lapis semiconductor co., ltd. 2-4-8 shinyokohama, kouhoku-ku, yokohama 222-8575, japan http://www.lapis-semi.com/en/ |
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